/* * * Call the FSP to do memory init. The FSP doesn't return to this function. * The FSP returns to the romstage_main_continue(). * */ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr) { FSP_INIT_RT_BUFFER *pFspRtBuffer = FspInitParams->RtBufferPtr; #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) UPD_DATA_REGION *fsp_upd_data = pFspRtBuffer->Common.UpdDataRgnPtr; #else MEM_CONFIG MemoryConfig; memset((void*)&MemoryConfig, 0, sizeof(MEM_CONFIG)); #endif FspInitParams->NvsBufferPtr = NULL; #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) /* Initialize the UPD Data */ GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data); ConfigureDefaultUpdData(fsp_upd_data); #else pFspRtBuffer->Platform.MemoryConfig = &MemoryConfig; pFspRtBuffer->PlatformConfiguration.PlatformConfig = &DefaultPlatformConfig; #endif #if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) /* Find the fastboot cache that was saved in the ROM */ FspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif pFspRtBuffer->Common.BootMode = 0; }
/* Set up the Broadwell-DE specific structures for the call into the FSP */ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr) { FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; /* Initialize the UPD Data */ GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif return; }
/* Set up the Rangeley specific structures for the call into the FSP */ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr) { FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; /* Initialize the UPD Data */ GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); return; }
/* Set up the Baytrail specific structures for the call into the FSP */ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr) { FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; uint32_t prev_sleep_state; /* Get previous sleep state but don't clear */ prev_sleep_state = chipset_prev_sleep_state(0); printk(BIOS_INFO, "prev_sleep_state = S%d\n", prev_sleep_state); /* Initialize the UPD Data */ GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif if (prev_sleep_state == 3) { /* S3 resume */ if ( pFspInitParams->NvsBufferPtr == NULL) { /* If waking from S3 and no cache then. */ printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); /* Clear Sleep Type */ outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); /* Reboot */ printk(BIOS_WARNING,"Rebooting..\n" ); warm_reset(); /* Should not reach here.. */ die("Reboot System\n"); } pFspRtBuffer->Common.BootMode = BOOT_ON_S3_RESUME; } else { /* Not S3 resume */ pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; } return; }