static int probe_setup_port(struct fintek_8250 *pdata, struct uart_8250_port *uart) { static const u16 addr[] = {0x4e, 0x2e}; static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67}; struct irq_data *irq_data; bool level_mode = false; int i, j, k, min, max; for (i = 0; i < ARRAY_SIZE(addr); i++) { for (j = 0; j < ARRAY_SIZE(keys); j++) { pdata->base_port = addr[i]; pdata->key = keys[j]; if (fintek_8250_enter_key(addr[i], keys[j])) continue; if (fintek_8250_check_id(pdata) || fintek_8250_get_ldn_range(pdata, &min, &max)) { fintek_8250_exit_key(addr[i]); continue; } for (k = min; k < max; k++) { u16 aux; sio_write_reg(pdata, LDN, k); aux = sio_read_reg(pdata, IO_ADDR1); aux |= sio_read_reg(pdata, IO_ADDR2) << 8; if (aux != uart->port.iobase) continue; pdata->index = k; irq_data = irq_get_irq_data(uart->port.irq); if (irq_data) level_mode = irqd_is_level_type(irq_data); fintek_8250_set_irq_mode(pdata, level_mode); fintek_8250_set_max_fifo(pdata); fintek_8250_goto_highspeed(uart, pdata); fintek_8250_exit_key(addr[i]); return 0; } fintek_8250_exit_key(addr[i]); } } return -ENODEV; }
static int find_base_port(struct fintek_8250 *pdata, u16 io_address) { static const u16 addr[] = {0x4e, 0x2e}; static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67}; int i, j, k; for (i = 0; i < ARRAY_SIZE(addr); i++) { for (j = 0; j < ARRAY_SIZE(keys); j++) { if (fintek_8250_enter_key(addr[i], keys[j])) continue; if (fintek_8250_check_id(addr[i])) { fintek_8250_exit_key(addr[i]); continue; } for (k = 0; k < 4; k++) { u16 aux; outb(LDN, addr[i] + ADDR_PORT); outb(k, addr[i] + DATA_PORT); outb(IO_ADDR1, addr[i] + ADDR_PORT); aux = inb(addr[i] + DATA_PORT); outb(IO_ADDR2, addr[i] + ADDR_PORT); aux |= inb(addr[i] + DATA_PORT) << 8; if (aux != io_address) continue; fintek_8250_exit_key(addr[i]); pdata->key = keys[j]; pdata->base_port = addr[i]; pdata->index = k; return 0; } fintek_8250_exit_key(addr[i]); } } return -ENODEV; }
static int fintek_8250_rs485_config(struct uart_port *port, struct serial_rs485 *rs485) { uint8_t config = 0; struct fintek_8250 *pdata = port->private_data; if (!pdata) return -EINVAL; if (rs485->flags & SER_RS485_ENABLED) memset(rs485->padding, 0, sizeof(rs485->padding)); else memset(rs485, 0, sizeof(*rs485)); rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND; if (rs485->delay_rts_before_send) { rs485->delay_rts_before_send = 1; config |= TXW4C_IRA; } if (rs485->delay_rts_after_send) { rs485->delay_rts_after_send = 1; config |= RXW4C_IRA; } if ((!!(rs485->flags & SER_RS485_RTS_ON_SEND)) == (!!(rs485->flags & SER_RS485_RTS_AFTER_SEND))) rs485->flags &= SER_RS485_ENABLED; else config |= RS485_URA; if (rs485->flags & SER_RS485_RTS_ON_SEND) config |= RTS_INVERT; if (fintek_8250_enter_key(pdata->base_port, pdata->key)) return -EBUSY; outb(LDN, pdata->base_port + ADDR_PORT); outb(pdata->index, pdata->base_port + DATA_PORT); outb(RS485, pdata->base_port + ADDR_PORT); outb(config, pdata->base_port + DATA_PORT); fintek_8250_exit_key(pdata->base_port); port->rs485 = *rs485; return 0; }
static int fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool level_mode) { int status; u8 tmp; status = fintek_8250_enter_key(pdata->base_port, pdata->key); if (status) return status; outb(LDN, pdata->base_port + ADDR_PORT); outb(pdata->index, pdata->base_port + DATA_PORT); outb(FINTEK_IRQ_MODE, pdata->base_port + ADDR_PORT); tmp = inb(pdata->base_port + DATA_PORT); tmp &= ~IRQ_MODE_MASK; tmp |= IRQ_SHARE; if (!level_mode) tmp |= IRQ_EDGE_HIGH; outb(tmp, pdata->base_port + DATA_PORT); fintek_8250_exit_key(pdata->base_port); return 0; }