static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
{
//#
//# Set the Synchronous clock division ratio for each clock domain
//#
pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);
//#
//# Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
//#
#if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
#elif ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
flashc_set_flash_waitstate_and_readmode(param->cpu_f);
#endif
//#
//# Switch the main clock source to the selected clock.
//#
pm_set_mclk_source(main_clk_src);
return PASS;
}
long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
{
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
if(PCL_OSC0 == osc)
{
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency,
// enable the OSC0, set the main clock source as being OSC0.
pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
}
else
{
return PCL_NOT_SUPPORTED;
}
#else
// Implementation for UC3C, UC3L parts.
#if AVR32_PM_VERSION_RESETVALUE < 0x400
return PCL_NOT_SUPPORTED;
#else
if(PCL_OSC0 == osc)
{
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, startup, true);
// Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
#if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
flashcdw_set_flash_waitstate_and_readmode(fcrystal);
#elif ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
flashc_set_flash_waitstate_and_readmode(fcrystal);
#endif
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
}
else
{
return PCL_NOT_SUPPORTED;
}
#endif
#endif
return PASS;
}
static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
{
//#
//# Set the Synchronous clock division ratio for each clock domain
//#
pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);
//#
//# Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
//#
#if UC3L
flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
#elif UC3C
flashc_set_flash_waitstate_and_readmode(param->cpu_f);
#endif
//#
//# Switch the main clock source to the selected clock.
//#
pm_set_mclk_source(main_clk_src);
return PASS;
}
static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)
{
#define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
#define AVR32_PM_PBA_MAX_FREQ 66000000
#define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000
#define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000
// Implementation for UC3C parts.
// Supported frequencies:
// Fosc0 mul div PLL div2_en cpu_f pba_f Comment
// 12 15 1 192 1 12 12
// 12 9 3 40 1 20 20 PLL out of spec
// 12 15 1 192 1 24 12
// 12 9 1 120 1 30 15
// 12 9 3 40 0 40 20 PLL out of spec
// 12 15 1 192 1 48 12
// 12 15 1 192 1 48 24
// 12 8 1 108 1 54 27
// 12 9 1 120 1 60 15
// 12 9 1 120 1 60 30
// 12 10 1 132 1 66 16.5
//
unsigned long in_cpu_f = param->cpu_f;
unsigned long in_osc0_f = param->osc0_f;
unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
unsigned long pll_freq, rest;
Bool b_div2_pba, b_div2_cpu;
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Start with CPU freq config
if (in_cpu_f == in_osc0_f)
{
param->cpu_f = in_osc0_f;
param->pba_f = in_osc0_f;
return PASS;
}
else if (in_cpu_f < in_osc0_f)
{
// TBD
}
rest = in_cpu_f % in_osc0_f;
for (div = 1; div < 32; div++)
{
if ((div * rest) % in_osc0_f == 0)
break;
}
if (div == 32)
return FAIL;
mul = (in_cpu_f * div) / in_osc0_f;
if (mul > PM_MAX_MUL)
return FAIL;
// export 2power from PLL div to div2_cpu
while (!(div % 2))
{
div /= 2;
div2_cpu++;
}
// Here we know the mul and div parameter of the PLL config.
// . Check out if the PLL has a valid in_cpu_f.
// . Try to have for the PLL frequency (VCO output) the highest possible value
// to reduce jitter.
while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
{
if (2 * mul > PM_MAX_MUL)
break;
mul *= 2;
div2_cpu++;
}
if (div2_cpu != 0)
{
div2_cpu--;
div2_en = 1;
}
pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
// Update real CPU Frequency
param->cpu_f = pll_freq / (1 << div2_cpu);
mul--;
scif_pll_opt_t opt;
opt.osc = SCIF_OSC0, // Sel Osc0 or Osc1
opt.lockcount = 16, // lockcount in main clock for the PLL wait lock
opt.div = div, // DIV=1 in the formula
opt.mul = mul, // MUL=7 in the formula
opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
rest = pll_freq;
while (rest > AVR32_PM_PBA_MAX_FREQ ||
rest != param->pba_f)
{
div2_pba++;
rest = pll_freq / (1 << div2_pba);
if (rest < param->pba_f)
break;
}
// Update real PBA Frequency
param->pba_f = pll_freq / (1 << div2_pba);
if (div2_cpu)
{
b_div2_cpu = TRUE;
div2_cpu--;
}
else
b_div2_cpu = FALSE;
if (div2_pba)
{
b_div2_pba = TRUE;
div2_pba--;
}
else
b_div2_pba = FALSE;
if (b_div2_cpu == TRUE )
{
pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU
pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB
pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB
}
if (b_div2_pba == TRUE )
{
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA
pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC
}
// Set Flashc Wait State
flashc_set_flash_waitstate_and_readmode(param->cpu_f);
// Set the main clock source as being PLL0.
pm_set_mclk_source(PM_CLK_SRC_PLL0);
return PASS;
}
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
// Replace "scif_configure_osc_crystalmode(SCIF_OSC0, 16000000)" by
// inline routine to safe code (160B)
{
typedef union
{
unsigned long oscctrl[2];
avr32_scif_oscctrl_t OSCCTRL[2];
} u_avr32_scif_oscctrl_t;
u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl;
// Read Register
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0] = AVR32_SCIF.OSCCTRL[SCIF_OSC0] ;
// Modify : Configure the oscillator mode to crystal and set the gain according to the
// crystal frequency.
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].gain =
(16000000 < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
(16000000 < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
(16000000 < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
AVR32_SCIF_OSCCTRL0_GAIN_G3;
AVR32_ENTER_CRITICAL_REGION( );
// Unlock the write-protected OSCCTRL0 register
SCIF_UNLOCK(AVR32_SCIF_OSCCTRL);
// Write Back
AVR32_SCIF.OSCCTRL[SCIF_OSC0] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0];
AVR32_LEAVE_CRITICAL_REGION( );
}
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC, true);
flashc_set_flash_waitstate_and_readmode(16000000);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 5;
break;
case 16000000:
mul = 2;
break;
case 12000000:
default:
mul = 3;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 0;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll_setup(SCIF_PLL0, &opt);
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0);
// Use 1 flash wait state
flashc_set_wait_state(1);
// Switch the main clock to PLL0
pm_set_mclk_source(PM_CLK_SRC_PLL0);
// fCPU: 48 MHz // USBC request a CPU clock >25MHz
// fPBA: 48 MHz
// fHSB: 48 MHz
// fPBB: 48 MHz must be the same that CPU
// fPBC: 48 MHz
pm_disable_clk_domain_div(PM_CLK_DOMAIN_0); // CPU
pm_disable_clk_domain_div(PM_CLK_DOMAIN_1); // HSB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_2); // PBA
pm_disable_clk_domain_div(PM_CLK_DOMAIN_3); // PBB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_4); // PBC
// Use 0 flash wait state
flashc_set_wait_state(1);
}
