void main(void)
{
/* Init UART */
fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200);
/* Enable interrupts */
fnet_cpu_irq_enable(0);
/* Run application */
fapp_main();
}
fnet_int32_t main (void)
{
/* Init UART. */
fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200u);
/* Enable Interrupts.*/
fnet_cpu_irq_enable(0u);
/* Run application. */
fapp_main();
return(0);
}
static void FnetTask()
{
// Delay the start of FNET
OSA_TimeDelay(5000);
/* Init UART. */
fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200);
/* Enable Interrupts.*/
fnet_cpu_irq_enable(0);
/* Run FNET application. - Function does not return */
fapp_main();
while(1){OSA_TimeDelay(1000);}
}
/************************************************************************
* NAME: cfm_command
*
* DESCRIPTION: CFM command
************************************************************************/
static void cfm_command( unsigned char command, unsigned long *address, unsigned long data )
{
fnet_cpu_irq_desc_t irq_desc;
irq_desc = fnet_cpu_irq_disable();
/* If the CFMCLKD register is written, the DIVLD bit is set. */
if((FNET_MCF_CFM_CFMCLKD & FNET_MCF_CFM_CFMCLKD_DIVLD) == 0)
{
/* CFM initialization. */
/* Prior to issuing any command, it is necessary to set
* the CFMCLKD register to divide the internal bus frequency
* to be within the 150- to 200-kHz range.
* NOTE: Setting CFMCLKD to a value such that FCLK < 150 KHz
* can destroy the flash memory due to overstress.
* Setting CFMCLKD to a value such that FCLK > 200 KHz can
* result in incomplete programming or erasure of the
* flash memory array cells.*/
if ((FNET_CFG_CPU_CLOCK_HZ/2) > 12800000) /* For bus frequencies greater than 12.8 MHz */
FNET_MCF_CFM_CFMCLKD = FNET_MCF_CFM_CFMCLKD_DIV((FNET_CFG_CPU_CLOCK_HZ/2)/8/200000)| FNET_MCF_CFM_CFMCLKD_PRDIV8;
else
FNET_MCF_CFM_CFMCLKD = FNET_MCF_CFM_CFMCLKD_DIV((FNET_CFG_CPU_CLOCK_HZ/2)/200000);
}
/* Write to one or more addresses in the flash memory.*/
#if !FNET_CFG_MCF_V1 /* Use the backdoor address. */
address = (unsigned long *)(FNET_CFG_MCF_IPSBAR+0x04000000+(unsigned long)address);
#endif
/* Use the frontdoor address. */
*address = data;
/* Write a valid command to the CFMCMD register. */
FNET_MCF_CFM_CFMCMD = command;
_cfm_command_lunch_inram();
fnet_cpu_irq_enable(irq_desc);
}
/************************************************************************
* NAME: fnet_ftfl_command
*
* DESCRIPTION: FTFL command
************************************************************************/
static void fnet_ftfl_command( fnet_uint8_t command, fnet_uint32_t *address, const fnet_uint8_t *data )
{
fnet_cpu_irq_desc_t irq_desc;
#if FNET_CFG_CPU_MK60N512 /* This problem exists in first-released-version product (mask set: 0M33Z). */
#if 0 /* For restoring.*/
fnet_uint32_t fmc_pfb0cr_reg = FNET_MK_FMC_PFB0CR;
fnet_uint32_t fmc_pfb1cr_reg = FNET_MK_FMC_PFB1CR;
#endif
/* Workaround: Allow pflash_only or pflash_only with pflash_swap
* configurations but disable speculation when in these configurations
* (via programming PFB0CR and PFB1CR's [2:1] bits to 2'h0."*/
FNET_MK_FMC_PFB0CR &= 0xFFFFFFE6; /* Single entry buffer disable.*/
FNET_MK_FMC_PFB1CR &= 0xFFFFFFE6; /* Single entry buffer disable. */
FNET_MK_FMC_PFB0CR &= 0xFFFFFFF9; /* Data Cache disable. */
FNET_MK_FMC_PFB1CR &= 0xFFFFFFF9; /* Data Cache disable. */
/* Just more info about the issue (Lozano Alejandro):
* I think what we are looking is silicon bug of P2 1.0 with mask set "0M33Z".
* The Platform Bank 0 Control Register (FMC_PFB0CR) and Platform Bank 1 Control Register
* (FMC_PFB1CR) provide cache control to the FlexMemory space. PFB0CR[4:3,0] controls
* bank0/Code Flash cache functionality, and PFB1CR[4:3,0] controls bank1/Data Flash cache
* functionality. The FMC comes out of reset with full cache functionality enabled for both flash banks.
* Due to a logic error, cache functionality cannot be permitted in pflash_only or pflash_only
* with pflash_swap configurations with total pflash size equal to 384KB or 512KB.
* Pflash_only sized with total pflash size equal to 128KB, 192KB or 256KB have correct
* cache functionality.
* The logic error allows cache aliasing to occur when performing accesses 256KB apart
* in pflash_only or pflash_only with pflash_swap configurations sized at 384KB or 512KB.
* E.G. An access to 0x0_eb00 (bank0 access) subsequent to an access to 0x5_eb00 (bank1 access)
* will erroneously hit and return the pflash cache's 0x5_eb00 read data.
*
* The Platform Bank 0 Control Register (FMC_PFB0CR) and Platform Bank 1 Control Register (FMC_PFB1CR) provide speculation control to the FlexMemory space. FMC_PFB0CR[2:1] controls bank0/Code Flash speculation functionality, and FMC_PFB1CR[2:1] controls bank1/Data Flash speculation functionality. The FMC comes out of reset with full speculation functionality enabled for both flash banks.
*
* Due to a logic error, speculation functionality cannot be permitted in pflash_only or pflash_only with pflash_swap configurations. (It is available in the FlexMem configuration.)
* The logic error allows speculation aliasing to occur in pflash_only or pflash_only with pflash_swap configurations.
*
* In pfonly total size 512K, aliasing occurs between accesses 256KB apart.
* In pfonly total size 384KB, (pfswap illegal), aliasing occurs between
* accesses in the first 128KB and the last 128KB.
* In pfonly total size 256KB, aliasing occurs between accesses 128KB apart.
* In pfonly total size 192KB, (pfswap illegal), aliasing occurs between
* accesses in the first 64KB and the last 64KB.
* In pfonly total size 128KB, aliasing occurs between accesses 64KB part.
*/
#if 0 /* Old Version.*/
/* This problem exists in first released version product (mask set: 0M33Z). It is proved.
* It is solved in next released version product (mask set: 0N30D) (do not have this mask set => not able to check it).
*/
FNET_MK_FMC_PFB0CR &= 0xFFFFFFFE; /* Single entry buffer disable.*/
FNET_MK_FMC_PFB1CR &= 0xFFFFFFFE; /* Single entry buffer disable. */
FNET_MK_FMC_PFB0CR &= 0xFFFFFFEF; /* Data Cache disable. */
FNET_MK_FMC_PFB1CR &= 0xFFFFFFEF; /* Data Cache disable. */
#endif
#endif
irq_desc = fnet_cpu_irq_disable();
/* The CCIF flag must read 1 to verify that any previous command has
* completed. If CCIF is zero, the previous command execution is still active, a new
* command write sequence cannot be started, and all writes to the FCCOB registers are
* ignored.
*/
while ((FNET_MK_FTFL_FSTAT & FNET_MK_FTFL_FSTAT_CCIF_MASK) == 0u)
{}
/* Ensure that the ACCERR and FPVIOL bits in the FSTAT register are cleared prior to
* starting the command write sequence.
*/
FNET_MK_FTFL_FSTAT = (FNET_MK_FTFL_FSTAT_ACCERR_MASK | FNET_MK_FTFL_FSTAT_FPVIOL_MASK);
/* The FCCOB register group uses a big endian addressing convention. */
/* Write a valid command to the FCCOB0 register. */
FNET_MK_FTFL_FCCOB0 = command;
/* Flash address.*/
FNET_MK_FTFL_FCCOB1 = (fnet_uint8_t)(((fnet_uint32_t)address) >> 16); /* Flash address [23:16] */
FNET_MK_FTFL_FCCOB2 = (fnet_uint8_t)(((fnet_uint32_t)address) >> 8); /* Flash address [15:8] */
FNET_MK_FTFL_FCCOB3 = (fnet_uint8_t)((fnet_uint32_t)address); /* Flash address [7:0] */
/* Data.*/
FNET_MK_FTFL_FCCOB4 = (fnet_uint8_t)(*(data+3)); /* Data Byte 0.*/
FNET_MK_FTFL_FCCOB5 = (fnet_uint8_t)(*(data+2)); /* Data Byte 1.*/
FNET_MK_FTFL_FCCOB6 = (fnet_uint8_t)(*(data+1)); /* Data Byte 2.*/
FNET_MK_FTFL_FCCOB7 = (fnet_uint8_t)(*data); /* Data Byte 3.*/
#if FNET_CFG_CPU_FLASH_PROGRAM_SIZE == 8u /* K70 */
if(command == FNET_MK_FNET_FTFL_FCCOB0_CMD_PROGRAM_PHRASE)
{
FNET_MK_FTFL_FCCOB8 = (fnet_uint8_t)(*(data+7));
FNET_MK_FTFL_FCCOB9 = (fnet_uint8_t)(*(data+6));
FNET_MK_FTFL_FCCOBA = (fnet_uint8_t)(*(data+5));
FNET_MK_FTFL_FCCOBB = (fnet_uint8_t)(*(data+4));
}
#endif
#if FNET_MK_FLASH_RAM_SECTION
fnet_ftfl_command_lunch_inram();
#else
/* To be sure that the function is alreday in ram.*/
if(fnet_ftfl_command_lunch_inram_ptr == FNET_NULL)
{
fnet_ftfl_command_lunch_inram_ptr = (void(*)(void))fnet_memcpy_func(fnet_ftfl_command_lunch_inram_buf,
(const fnet_uint8_t *)(fnet_ftfl_command_lunch_inram),
/* sizeof(fnet_ftfl_command_lunch_inram_buf)*/
(fnet_size_t)fnet_ftfl_command_lunch_inram_end - (fnet_size_t)fnet_ftfl_command_lunch_inram );
}
fnet_ftfl_command_lunch_inram_ptr();
#endif
#if 0 /* FNET_CFG_CPU_MK60N512*/ /* Restore FMC registers.*/
FNET_MK_FMC_PFB0CR = fmc_pfb0cr_reg;
FNET_MK_FMC_PFB1CR = fmc_pfb1cr_reg;
#endif
fnet_cpu_irq_enable(irq_desc);
}
