int mv_load_fpga(void)
{
int result;
size_t data_size = 0;
void *fpga_data = NULL;
char *datastr = getenv("fpgadata");
char *sizestr = getenv("fpgadatasize");
if (getenv("skip_fpga")) {
printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
return -1;
}
printf("loading FPGA\n");
if (datastr)
fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
if (sizestr)
data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
if (!data_size) {
printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
return -1;
}
result = fpga_load(0, fpga_data, data_size);
if (!result)
show_boot_progress(0);
return result;
}
int mv_load_fpga(void)
{
int result;
size_t data_size = 0;
void *fpga_data = NULL;
char *datastr = getenv("fpgadata");
char *sizestr = getenv("fpgadatasize");
if (getenv("skip_fpga")) {
printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
return -1;
}
printf("loading FPGA\n");
if (datastr)
fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
if (sizestr)
data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
if (!data_size) {
printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
return -1;
}
result = fpga_load(0, fpga_data, data_size, BIT_FULL);
if (!result)
bootstage_mark(BOOTSTAGE_ID_START);
return result;
}
static int mmc_load_fpga_image_fat(struct mmc *mmc)
{
int err;
int devnum = 0;
const fpga_desc *const desc = fpga_get_desc(devnum);
Xilinx_desc *desc_xilinx = desc->devdesc;
/* FIXME = standard file size + header desc_xilinx->size + 0x6c */
err = file_fat_read(CONFIG_SPL_FPGA_LOAD_ARGS_NAME,
(void *)CONFIG_SPL_FPGA_LOAD_ADDR,
0);
if (err <= 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("spl: error reading image %s, err - %d\n",
CONFIG_SPL_FPGA_LOAD_ARGS_NAME, err);
#endif
return -1;
}
#ifdef CONFIG_SPL_FPGA_BIT
return fpga_loadbitstream(devnum, (char *)CONFIG_SPL_FPGA_LOAD_ADDR,
desc_xilinx->size, BIT_FULL);
#else
return fpga_load(devnum, (const void *)CONFIG_SPL_FPGA_LOAD_ADDR,
desc_xilinx->size, BIT_FULL);
#endif
}
int fpga_init (void)
{
ulong addr;
ulong new_id, old_id = 0;
image_header_t *hdr;
fpga_t* fpga;
int do_load, i, j;
char name[16], *s;
/*
* Port setup for FPGA control
*/
for (i = 0; i < fpga_count; i++) {
fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
}
/*
* Load FPGA(s): a new net-list is loaded if the FPGA is
* empty, Power-on-Reset or the old one is not up-to-date
*/
for (i = 0; i < fpga_count; i++) {
fpga = &fpga_list[i];
printf ("%s: ", fpga->name);
for (j = 0; j < strlen(fpga->name); j++)
name[j] = tolower(fpga->name[j]);
name[j] = '\0';
sprintf(name, "%s_addr", name);
addr = 0;
if ((s = getenv(name)) != NULL)
addr = simple_strtoul(s, NULL, 16);
if (!addr) {
printf ("env. variable %s undefined\n", name);
return 1;
}
hdr = (image_header_t *)addr;
if ((new_id = fpga_get_version(fpga, hdr->ih_name)) == -1)
return 1;
do_load = 1;
if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
old_id = fpga_control(fpga, FPGA_GET_ID);
if (new_id == old_id)
do_load = 0;
}
if (do_load) {
printf ("loading ");
fpga_load (fpga, addr, 0);
} else {
printf ("loaded (%08lx)\n", old_id);
}
}
return 0;
}
int
do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if 0
int rc;
#endif
#ifdef CONFIG_ETHER_LOOPBACK_TEST
extern void eth_loopback_test (void);
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
#if 0
/* Load FPGA with test program */
printf ("Loading test FPGA program ...");
rc = fpga_load (0, test_bitfile, sizeof (test_bitfile));
switch (rc) {
case LOAD_SUCCESS:
printf (" SUCCEEDED\n");
break;
case LOAD_FAIL_NOCONF:
printf (" FAILED (no configuration space defined)\n");
return 1;
case LOAD_FAIL_NOINIT:
printf (" FAILED (timeout - no INIT signal seen)\n");
return 1;
case LOAD_FAIL_NODONE:
printf (" FAILED (timeout - no DONE signal seen)\n");
return 1;
default:
printf (" FAILED (unknown return code from fpga_load\n");
return 1;
}
/* run Local Bus <=> Xilinx tests */
/* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
/* run SDRAM test */
#endif
#ifdef CONFIG_ETHER_LOOPBACK_TEST
/* run Ethernet test */
eth_loopback_test ();
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
return 0;
}
int mvblm7_load_fpga(void)
{
size_t data_size = 0;
void *fpga_data = NULL;
char *datastr = getenv("fpgadata");
char *sizestr = getenv("fpgadatasize");
if (datastr)
fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
if (sizestr)
data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
return fpga_load(0, fpga_data, data_size);
}
int
main(void)
{
printf("\nBoot\n");
EEInit();
SPI_InitFlash();
#ifdef TSC_FPGA
fpga_load();
#endif
EMAC_Init();
LoadBootCommands();
if (getc(1) == -1) {
start_wdog(30);
ExecuteEnvironmentFunctions();
}
Bootloader(getc);
return (1);
}
int main(int argc, char *argv[])
{
const struct astribank_type *abtype;
struct my_usb_device mydev;
const char *devpath = NULL;
const char *binfile = NULL;
const char *inhexfile = NULL;
const char *outhexfile = NULL;
struct hexdata *hexdata = NULL;
int opt_reset = 0;
int opt_info = 0;
int opt_read_eeprom = 0;
int opt_output_width = 0;
int output_is_set = 0;
#ifdef XORCOM_INTERNAL
int opt_write_eeprom = 0;
char *vendor = NULL;
char *source = NULL;
char *product = NULL;
char *release = NULL;
char *label = NULL;
const char options[] = "rib:D:ghH:I:vw:C:V:P:R:S:";
#else
const char options[] = "rib:D:ghH:I:vw:";
#endif
int ret = 0;
progname = argv[0];
assert(sizeof(struct fpga_packet_header) <= PACKET_SIZE);
assert(sizeof(struct myeeprom) == EEPROM_SIZE);
while (1) {
int c;
c = getopt (argc, argv, options);
if (c == -1)
break;
switch (c) {
case 'D':
devpath = optarg;
if(output_is_set++) {
ERR("Cannot set -D. Another output option is already selected\n");
return 1;
}
break;
case 'r':
opt_reset = 1;
break;
case 'i':
opt_info = 1;
break;
case 'b':
binfile = optarg;
if(output_is_set++) {
ERR("Cannot set -b. Another output option is already selected\n");
return 1;
}
break;
case 'g':
opt_read_eeprom = 1;
break;
case 'H':
outhexfile = optarg;
if(output_is_set++) {
ERR("Cannot set -H. Another output option is already selected\n");
return 1;
}
break;
case 'I':
inhexfile = optarg;
break;
#ifdef XORCOM_INTERNAL
case 'V':
vendor = optarg;
break;
case 'C':
source = optarg;
break;
case 'P':
product = optarg;
break;
case 'R':
release = optarg;
break;
case 'S':
label = optarg;
{
const char GOOD_CHARS[] =
"abcdefghijklmnopqrstuvwxyz"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"0123456789"
"-_.";
int len = strlen(label);
int goodlen = strspn(label, GOOD_CHARS);
if(len > LABEL_SIZE) {
ERR("Label too long (%d > %d)\n", len, LABEL_SIZE);
usage();
}
if(goodlen != len) {
ERR("Bad character in label number (pos=%d)\n", goodlen);
usage();
}
}
break;
#endif
case 'w':
opt_output_width = strtoul(optarg, NULL, 0);
break;
case 'v':
verbose++;
break;
case 'h':
default:
ERR("Unknown option '%c'\n", c);
usage();
}
}
if (optind != argc) {
usage();
}
if(inhexfile) {
#ifdef XORCOM_INTERNAL
if(vendor || product || release || label || source ) {
ERR("The -I option is exclusive of -[VPRSC]\n");
return 1;
}
#endif
parse_hexfile_set_reporting(parse_report_func);
hexdata = parse_hexfile(inhexfile, MAX_HEX_LINES);
if(!hexdata) {
ERR("Bailing out\n");
exit(1);
}
if(opt_info) {
printf("%s: Version=%s Checksum=%d\n",
inhexfile, hexdata->version_info,
bsd_checksum(hexdata));
}
if(binfile) {
dump_binary(hexdata, binfile);
return 0;
}
if(outhexfile) {
if(opt_output_width)
dump_hexfile2(hexdata, outhexfile, opt_output_width);
else
dump_hexfile(hexdata, outhexfile);
return 0;
}
}
#ifdef XORCOM_INTERNAL
else if(vendor || product || release || label || source ) {
if(outhexfile) {
FILE *fp;
if(strcmp(outhexfile, "-") == 0)
fp = stdout;
else if((fp = fopen(outhexfile, "w")) == NULL) {
perror(outhexfile);
return 1;
}
memset(&mydev.eeprom, 0, sizeof(struct myeeprom));
eeprom_fill(&mydev.eeprom, vendor, product, release, label, source);
gen_hexline((uint8_t *)&mydev.eeprom, 0, sizeof(mydev.eeprom), fp);
gen_hexline(NULL, 0, 0, fp); /* EOF */
return 0;
}
}
#endif
if(!devpath) {
ERR("Missing device path\n");
usage();
}
DBG("Startup %s\n", devpath);
if((abtype = my_usb_device_identify(devpath, &mydev)) == NULL) {
ERR("Bad device. Does not match our types.\n");
usage();
}
INFO("FIRMWARE: %s (type=%d)\n", abtype->name, abtype->type_code);
if(!my_usb_device_init(devpath, &mydev, abtype)) {
ERR("Failed to initialize USB device '%s'\n", devpath);
ret = -ENODEV;
goto dev_err;
}
ret = eeprom_get(&mydev);
if(ret < 0) {
ERR("Failed reading eeprom\n");
goto dev_err;
}
#ifdef XORCOM_INTERNAL
if(vendor || product || release || label || source ) {
eeprom_fill(&mydev.eeprom, vendor, product, release, label, source);
opt_write_eeprom = 1;
opt_read_eeprom = 1;
}
#endif
if(opt_read_eeprom) {
show_device_info(&mydev);
}
if(hexdata) {
if (!mydev.is_usb2)
INFO("Warning: working on a low end USB1 backend\n");
if(!fpga_load(&mydev, hexdata)) {
ERR("FPGA loading failed\n");
ret = -ENODEV;
goto dev_err;
}
ret = renumerate_device(&mydev, PT_RENUMERATE);
if(ret < 0) {
ERR("Renumeration failed: errno=%d\n", ret);
goto dev_err;
}
}
#ifdef XORCOM_INTERNAL
else if(opt_write_eeprom) {
if(abtype->type_code == USB_FIRMWARE_II) {
ERR("No EEPROM burning command in %s. Use fxload for that\n",
abtype->name);
goto dev_err;
}
ret = eeprom_set(&mydev, &mydev.eeprom);
if(ret < 0) {
ERR("Failed writing eeprom: %s\n", strerror(-ret));
goto dev_err;
}
printf("------- RESULTS -------\n");
show_device_info(&mydev);
}
#endif
if(opt_reset) {
DBG("Reseting to default\n");
ret = renumerate_device(&mydev, PT_RESET);
if(ret < 0) {
ERR("Renumeration to default failed: errno=%d\n", ret);
goto dev_err;
}
}
DBG("Exiting\n");
dev_err:
my_usb_device_cleanup(&mydev);
return ret;
}
int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
uint8_t arch, const ulong *ld_start, ulong * const ld_len)
{
ulong tmp_img_addr, img_data, img_len;
void *buf;
int conf_noffset;
int fit_img_result;
char *uname, *name;
int err;
int devnum = 0; /* TODO support multi fpga platforms */
const fpga_desc * const desc = fpga_get_desc(devnum);
xilinx_desc *desc_xilinx = desc->devdesc;
/* Check to see if the images struct has a FIT configuration */
if (!genimg_has_config(images)) {
debug("## FIT configuration was not specified\n");
return 0;
}
/*
* Obtain the os FIT header from the images struct
* copy from dataflash if needed
*/
tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
tmp_img_addr = genimg_get_image(tmp_img_addr);
buf = map_sysmem(tmp_img_addr, 0);
/*
* Check image type. For FIT images get FIT node
* and attempt to locate a generic binary.
*/
switch (genimg_get_format(buf)) {
case IMAGE_FORMAT_FIT:
conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
err = fdt_get_string_index(buf, conf_noffset, FIT_FPGA_PROP, 0,
(const char **)&uname);
if (err < 0) {
debug("## FPGA image is not specified\n");
return 0;
}
fit_img_result = fit_image_load(images,
tmp_img_addr,
(const char **)&uname,
&(images->fit_uname_cfg),
arch,
IH_TYPE_FPGA,
BOOTSTAGE_ID_FPGA_INIT,
FIT_LOAD_OPTIONAL_NON_ZERO,
&img_data, &img_len);
debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
uname, img_data, img_len);
if (fit_img_result < 0) {
/* Something went wrong! */
return fit_img_result;
}
if (img_len >= desc_xilinx->size) {
name = "full";
err = fpga_loadbitstream(devnum, (char *)img_data,
img_len, BIT_FULL);
if (err)
err = fpga_load(devnum, (const void *)img_data,
img_len, BIT_FULL);
} else {
name = "partial";
err = fpga_loadbitstream(devnum, (char *)img_data,
img_len, BIT_PARTIAL);
if (err)
err = fpga_load(devnum, (const void *)img_data,
img_len, BIT_PARTIAL);
}
printf(" Programming %s bitstream... ", name);
if (err)
printf("failed\n");
else
printf("OK\n");
break;
default:
printf("The given image format is not supported (corrupt?)\n");
return 1;
}
return 0;
}
/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
#if defined(CONFIG_FPGA_XILINX)
unsigned int length;
unsigned int swapsize;
char buffer[80];
unsigned char *dataptr;
unsigned int i;
int rc;
dataptr = (unsigned char *)fpgadata;
/* skip the first bytes of the bitsteam, their meaning is unknown */
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;
dataptr+=length;
/* get design name (identifier, length, string) */
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;
if (*dataptr++ != 0x61) {
debug("%s: Design name identifier not recognized "
"in bitstream\n",
__func__);
return FPGA_FAIL;
}
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;
for(i=0;i<length;i++)
buffer[i] = *dataptr++;
printf(" design filename = \"%s\"\n", buffer);
/* get part number (identifier, length, string) */
if (*dataptr++ != 0x62) {
printf("%s: Part number identifier not recognized "
"in bitstream\n",
__func__);
return FPGA_FAIL;
}
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;
for(i=0;i<length;i++)
buffer[i] = *dataptr++;
printf(" part number = \"%s\"\n", buffer);
/* get date (identifier, length, string) */
if (*dataptr++ != 0x63) {
printf("%s: Date identifier not recognized in bitstream\n",
__func__);
return FPGA_FAIL;
}
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;
for(i=0;i<length;i++)
buffer[i] = *dataptr++;
printf(" date = \"%s\"\n", buffer);
/* get time (identifier, length, string) */
if (*dataptr++ != 0x64) {
printf("%s: Time identifier not recognized in bitstream\n",
__func__);
return FPGA_FAIL;
}
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;
for(i=0;i<length;i++)
buffer[i] = *dataptr++;
printf(" time = \"%s\"\n", buffer);
/* get fpga data length (identifier, length) */
if (*dataptr++ != 0x65) {
printf("%s: Data length identifier not recognized in bitstream\n",
__func__);
return FPGA_FAIL;
}
swapsize = ((unsigned int) *dataptr <<24) +
((unsigned int) *(dataptr+1) <<16) +
((unsigned int) *(dataptr+2) <<8 ) +
((unsigned int) *(dataptr+3) ) ;
dataptr+=4;
printf(" bytes in bitstream = %d\n", swapsize);
rc = fpga_load(dev, dataptr, swapsize);
return rc;
#else
printf("Bitstream support only for Xilinx devices\n");
return FPGA_FAIL;
#endif
}
int main(void)
{
int i, fp_id, num_bytes, pagesize, buf_size, memali;
const char *loadfile = "top.bin.ufp";
err_e err, e;
void * bp;
u_64 val;
long long data[2][1024];
char line_in[256];
FILE* file;
char* filename;
int k;
printf("Start program\n");
filename="mas_input_int32.New.txt";
file = fopen(filename, "r");
if (file == NULL)
{
printf ("ERROR: Could not open input file %s for reading.\n", filename);
return(-1);
}
k=0;
while(fgets(line_in, 255, file) != NULL)
{
sscanf(line_in,"%ld %ld", &data[0][k],&data[1][k]);
if(data[0][k]<0) data[0][k]=-1*data[0][k];
if(data[1][k]<0) data[1][k]=-1*data[1][k];
if(k<5) printf("Data read = %d %d %d\n", k, data[0][k], data[1][k]);
k++;
}
// Set FPGA ready
fp_id = fpga_open("/dev/ufp0", O_RDWR|O_SYNC, &e);
num_bytes = fpga_load(fp_id, loadfile, &err);
fpga_reset(fp_id, &e);
fpga_start(fp_id, &e);
// Set RAMS ready
rams[0] = fpga_memmap(fp_id, MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, MEM_OFFSET + 0*MEM_DISTANCE, &e);
rams[1] = fpga_memmap(fp_id, MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, MEM_OFFSET + 1*MEM_DISTANCE, &e);
rams[2] = fpga_memmap(fp_id, MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, MEM_OFFSET + 2*MEM_DISTANCE, &e);
rams[3] = fpga_memmap(fp_id, MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, MEM_OFFSET + 3*MEM_DISTANCE, &e);
// Initalize vectors and input data on rams
u_64 word0 = (u_64) data[0][0];
u_64 word1 = (u_64) data[1][0];
u_64 word2 = 0;
u_64 *word_0 = rams[0];
u_64 *word_1 = rams[1];
u_64 *word_2 = rams[2];
for( i = 0; i < 128; i++)
{
*word_0 ++= (u_64) data[0][i];
*word_1 ++= (u_64) data[1][i];
*word_2 ++= 0;
}
// Set memory for FPGA use
pagesize = getpagesize();
buf_size = ((128*1024*1024 + (pagesize - 1)) / pagesize) * pagesize;
memali = posix_memalign(&bp, pagesize, buf_size);
fpga_register_ftrmem(fp_id, bp, buf_size, &e);
ftr_mem = bp;
// Setup Mitrion run
void * addr = ftr_mem;
fpga_wrt_appif_val(fp_id, 0x00000000000000001UL, (0x01*sizeof(u_64)) + 0, TYPE_VAL, &e);
fpga_wrt_appif_val(fp_id, 88, ((0x40+1)*sizeof(u_64)), TYPE_VAL, &e);
fpga_wrt_appif_val(fp_id, (u_64)addr, (0x40*sizeof(u_64)), TYPE_ADDR, &e);
fpga_wrt_appif_val(fp_id, 0x000000000000000000UL, (0x02 * sizeof(u_64)), TYPE_VAL, &e);
fpga_wrt_appif_val(fp_id, 0x000000000000000000UL, (0x01 * sizeof(u_64)), TYPE_VAL, &e);
// Loop and wait until FPGA calculation is done
do
{
fpga_rd_appif_val(fp_id, (void*)&val, (0x02 * sizeof(u_64)), &e);
} while((val&1) == 0);
// Print the final result
u_64 * word_dst = rams[3];
u_64 wordp = *word_dst;
for(i = 0;i < 128; i++)
{
wordp = *word_dst;
word_dst++;
printf("FPGA %d: %d + %d = %ld\n", i, data[0][i], data[1][i], wordp);
}
printf("End of program ");
return 0;
}
int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector, void *fit)
{
int sectors;
ulong size;
unsigned long count;
struct spl_image_info image_info;
int node = -1;
int images, ret;
int base_offset, hsize, align_len = ARCH_DMA_MINALIGN - 1;
int index = 0;
/*
* For FIT with external data, figure out where the external images
* start. This is the base for the data-offset properties in each
* image.
*/
size = fdt_totalsize(fit);
size = (size + 3) & ~3;
size = board_spl_fit_size_align(size);
base_offset = (size + 3) & ~3;
/*
* So far we only have one block of data from the FIT. Read the entire
* thing, including that first block, placing it so it finishes before
* where we will load the image.
*
* Note that we will load the image such that its first byte will be
* at the load address. Since that byte may be part-way through a
* block, we may load the image up to one block before the load
* address. So take account of that here by subtracting an addition
* block length from the FIT start position.
*
* In fact the FIT has its own load address, but we assume it cannot
* be before CONFIG_SYS_TEXT_BASE.
*
* For FIT with data embedded, data is loaded as part of FIT image.
* For FIT with external data, data is not loaded in this step.
*/
hsize = (size + info->bl_len + align_len) & ~align_len;
fit = spl_get_load_buffer(-hsize, hsize);
sectors = get_aligned_image_size(info, size, 0);
count = info->read(info, sector, sectors, fit);
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n",
sector, sectors, fit, count, size);
if (count == 0)
return -EIO;
/* find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
if (images < 0) {
debug("%s: Cannot find /images node: %d\n", __func__, images);
return -1;
}
#ifdef CONFIG_SPL_FPGA_SUPPORT
node = spl_fit_get_image_node(fit, images, "fpga", 0);
if (node >= 0) {
/* Load the image and set up the spl_image structure */
ret = spl_load_fit_image(info, sector, fit, base_offset, node,
spl_image);
if (ret) {
printf("%s: Cannot load the FPGA: %i\n", __func__, ret);
return ret;
}
debug("FPGA bitstream at: %x, size: %x\n",
(u32)spl_image->load_addr, spl_image->size);
ret = fpga_load(0, (const void *)spl_image->load_addr,
spl_image->size, BIT_FULL);
if (ret) {
printf("%s: Cannot load the image to the FPGA\n",
__func__);
return ret;
}
puts("FPGA image loaded from FIT\n");
node = -1;
}
#endif
/*
* Find the U-Boot image using the following search order:
* - start at 'firmware' (e.g. an ARM Trusted Firmware)
* - fall back 'kernel' (e.g. a Falcon-mode OS boot
* - fall back to using the first 'loadables' entry
*/
if (node < 0)
node = spl_fit_get_image_node(fit, images, FIT_FIRMWARE_PROP,
0);
#ifdef CONFIG_SPL_OS_BOOT
if (node < 0)
node = spl_fit_get_image_node(fit, images, FIT_KERNEL_PROP, 0);
#endif
if (node < 0) {
debug("could not find firmware image, trying loadables...\n");
node = spl_fit_get_image_node(fit, images, "loadables", 0);
/*
* If we pick the U-Boot image from "loadables", start at
* the second image when later loading additional images.
*/
index = 1;
}
if (node < 0) {
debug("%s: Cannot find u-boot image node: %d\n",
__func__, node);
return -1;
}
/* Load the image and set up the spl_image structure */
ret = spl_load_fit_image(info, sector, fit, base_offset, node,
spl_image);
if (ret)
return ret;
/*
* For backward compatibility, we treat the first node that is
* as a U-Boot image, if no OS-type has been declared.
*/
if (!spl_fit_image_get_os(fit, node, &spl_image->os))
debug("Image OS is %s\n", genimg_get_os_name(spl_image->os));
#if !defined(CONFIG_SPL_OS_BOOT)
else
spl_image->os = IH_OS_U_BOOT;
#endif
/*
* Booting a next-stage U-Boot may require us to append the FDT.
* We allow this to fail, as the U-Boot image might embed its FDT.
*/
if (spl_image->os == IH_OS_U_BOOT)
spl_fit_append_fdt(spl_image, info, sector, fit,
images, base_offset);
/* Now check if there are more images for us to load */
for (; ; index++) {
uint8_t os_type = IH_OS_INVALID;
node = spl_fit_get_image_node(fit, images, "loadables", index);
if (node < 0)
break;
ret = spl_load_fit_image(info, sector, fit, base_offset, node,
&image_info);
if (ret < 0)
continue;
if (!spl_fit_image_get_os(fit, node, &os_type))
debug("Loadable is %s\n", genimg_get_os_name(os_type));
if (os_type == IH_OS_U_BOOT) {
spl_fit_append_fdt(&image_info, info, sector,
fit, images, base_offset);
spl_image->fdt_addr = image_info.fdt_addr;
}
/*
* If the "firmware" image did not provide an entry point,
* use the first valid entry point from the loadables.
*/
if (spl_image->entry_point == FDT_ERROR &&
image_info.entry_point != FDT_ERROR)
spl_image->entry_point = image_info.entry_point;
/* Record our loadables into the FDT */
if (spl_image->fdt_addr)
spl_fit_record_loadable(fit, images, index,
spl_image->fdt_addr,
&image_info);
}
/*
* If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's
* Makefile will set it to 0 and it will end up as the entry point
* here. What it actually means is: use the load address.
*/
if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0)
spl_image->entry_point = spl_image->load_addr;
spl_image->flags |= SPL_FIT_FOUND;
#ifdef CONFIG_SECURE_BOOT
board_spl_fit_post_load((ulong)fit, size);
#endif
return 0;
}
/* ------------------------------------------------------------------------- */
int
do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
uchar *addr, *save_addr;
ulong size;
int mezz, arg, result;
switch (argc) {
case 0:
case 1:
break;
case 2:
if (strcmp (argv[1], "info") == 0) {
printf ("\nHymod FPGA Info...\n");
printf ("\t\t\t\tAddress\t\tSize\n");
printf ("\tMain Configuration:\t0x%08x\t%d\n",
FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
printf ("\tMain Register:\t\t0x%08x\t%d\n",
FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
printf ("\tMain Port:\t\t0x%08x\t%d\n",
FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
printf ("\tMezz Configuration:\t0x%08x\t%d\n",
FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
return 0;
}
break;
case 3:
if (strcmp (argv[1], "store") == 0) {
addr = (uchar *) simple_strtoul (argv[2], NULL, 16);
save_addr = addr;
#if 0
/* fpga readback unimplemented */
while (more readback data)
*addr++ = *fpga;
result = error ? STORE_FAIL_XXX : STORE_SUCCESS;
#else
result = STORE_SUCCESS;
#endif
if (result == STORE_SUCCESS) {
printf ("SUCCEEDED (%d bytes)\n",
addr - save_addr);
return 0;
} else
printf ("FAILED (%d bytes)\n",
addr - save_addr);
return 1;
}
break;
case 4:
if (strcmp (argv[1], "tftp") == 0) {
copy_filename (BootFile, argv[2], sizeof (BootFile));
load_addr = simple_strtoul (argv[3], NULL, 16);
NetBootFileXferSize = 0;
if (NetLoop (TFTP) <= 0) {
printf ("tftp transfer failed - aborting "
"fgpa load\n");
return 1;
}
if (NetBootFileXferSize == 0) {
printf ("can't determine file size - "
"aborting fpga load\n");
return 1;
}
printf ("File transfer succeeded - "
"beginning fpga load...");
result = fpga_load (0, (uchar *) load_addr,
NetBootFileXferSize);
if (result == LOAD_SUCCESS) {
printf ("SUCCEEDED\n");
return 0;
} else if (result == LOAD_FAIL_NOCONF)
printf ("FAILED (no CONF)\n");
else if (result == LOAD_FAIL_NOINIT)
printf ("FAILED (no INIT)\n");
else
printf ("FAILED (no DONE)\n");
return 1;
}
/* fall through ... */
case 5:
if (strcmp (argv[1], "load") == 0) {
if (argc == 5) {
if (strcmp (argv[2], "main") == 0)
mezz = 0;
else if (strcmp (argv[2], "mezz") == 0)
mezz = 1;
else {
printf ("FPGA type must be either "
"`main' or `mezz'\n");
return 1;
}
arg = 3;
} else {
mezz = 0;
arg = 2;
}
addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16);
size = (ulong) simple_strtoul (argv[arg], NULL, 16);
result = fpga_load (mezz, addr, size);
if (result == LOAD_SUCCESS) {
printf ("SUCCEEDED\n");
return 0;
} else if (result == LOAD_FAIL_NOCONF)
printf ("FAILED (no CONF)\n");
else if (result == LOAD_FAIL_NOINIT)
printf ("FAILED (no INIT)\n");
else
printf ("FAILED (no DONE)\n");
return 1;
}
break;
default:
break;
}
cmd_usage(cmdtp);
return 1;
}
int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong addr = 0;
int i;
fpga_t* fpga;
if (argc < 2)
goto failure;
if (strncmp(argv[1], "stat", 4) == 0) { /* status */
if (argc == 2) {
for (i = 0; i < fpga_count; i++) {
fpga_status (&fpga_list[i]);
}
}
else if (argc == 3) {
if ((fpga = fpga_get(argv[2])) == 0)
goto failure;
fpga_status (fpga);
}
else
goto failure;
}
else if (strcmp(argv[1],"load") == 0) { /* load */
if (argc == 3 && fpga_count == 1) {
fpga = &fpga_list[0];
}
else if (argc == 4) {
if ((fpga = fpga_get(argv[2])) == 0)
goto failure;
}
else
goto failure;
addr = simple_strtoul(argv[argc-1], NULL, 16);
printf ("FPGA load %s: addr %08lx: ",
fpga->name, addr);
fpga_load (fpga, addr, 1);
}
else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */
if (argc == 2 && fpga_count == 1) {
fpga = &fpga_list[0];
}
else if (argc == 3) {
if ((fpga = fpga_get(argv[2])) == 0)
goto failure;
}
else
goto failure;
printf ("FPGA reset %s: ", fpga->name);
if (fpga_reset(fpga))
printf ("ERROR: Timeout\n");
else
printf ("done\n");
}
else
goto failure;
return 0;
failure:
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/* command form:
* fpga <op> <device number> <data addr> <datasize>
* where op is 'load', 'dump', or 'info'
* If there is no device number field, the fpga environment variable is used.
* If there is no data addr field, the fpgadata environment variable is used.
* The info command requires no data address field.
*/
int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
int op, dev = FPGA_INVALID_DEVICE;
size_t data_size = 0;
void *fpga_data = NULL;
char *devstr = getenv("fpga");
char *datastr = getenv("fpgadata");
int rc = FPGA_FAIL;
int wrong_parms = 0;
#if defined(CONFIG_FIT)
const char *fit_uname = NULL;
ulong fit_addr;
#endif
#if defined(CONFIG_CMD_FPGA_LOADFS)
fpga_fs_info fpga_fsinfo;
fpga_fsinfo.fstype = FS_TYPE_ANY;
#endif
if (devstr)
dev = (int) simple_strtoul(devstr, NULL, 16);
if (datastr)
fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
switch (argc) {
#if defined(CONFIG_CMD_FPGA_LOADFS)
case 9:
fpga_fsinfo.blocksize = (unsigned int)
simple_strtoul(argv[5], NULL, 16);
fpga_fsinfo.interface = argv[6];
fpga_fsinfo.dev_part = argv[7];
fpga_fsinfo.filename = argv[8];
#endif
case 5: /* fpga <op> <dev> <data> <datasize> */
data_size = simple_strtoul(argv[4], NULL, 16);
case 4: /* fpga <op> <dev> <data> */
#if defined(CONFIG_FIT)
if (fit_parse_subimage(argv[3], (ulong)fpga_data,
&fit_addr, &fit_uname)) {
fpga_data = (void *)fit_addr;
debug("* fpga: subimage '%s' from FIT image ",
fit_uname);
debug("at 0x%08lx\n", fit_addr);
} else
#endif
{
fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
debug("* fpga: cmdline image address = 0x%08lx\n",
(ulong)fpga_data);
}
debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
case 3: /* fpga <op> <dev | data addr> */
dev = (int)simple_strtoul(argv[2], NULL, 16);
debug("%s: device = %d\n", __func__, dev);
/* FIXME - this is a really weak test */
if ((argc == 3) && (dev > fpga_count())) {
/* must be buffer ptr */
debug("%s: Assuming buffer pointer in arg 3\n",
__func__);
#if defined(CONFIG_FIT)
if (fit_parse_subimage(argv[2], (ulong)fpga_data,
&fit_addr, &fit_uname)) {
fpga_data = (void *)fit_addr;
debug("* fpga: subimage '%s' from FIT image ",
fit_uname);
debug("at 0x%08lx\n", fit_addr);
} else
#endif
{
fpga_data = (void *)(uintptr_t)dev;
debug("* fpga: cmdline image addr = 0x%08lx\n",
(ulong)fpga_data);
}
debug("%s: fpga_data = 0x%lx\n",
__func__, (ulong)fpga_data);
dev = FPGA_INVALID_DEVICE; /* reset device num */
}
case 2: /* fpga <op> */
op = (int)fpga_get_op(argv[1]);
break;
default:
debug("%s: Too many or too few args (%d)\n", __func__, argc);
op = FPGA_NONE; /* force usage display */
break;
}
if (dev == FPGA_INVALID_DEVICE) {
puts("FPGA device not specified\n");
op = FPGA_NONE;
}
switch (op) {
case FPGA_NONE:
case FPGA_INFO:
break;
#if defined(CONFIG_CMD_FPGA_LOADFS)
case FPGA_LOADFS:
/* Blocksize can be zero */
if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
!fpga_fsinfo.filename)
wrong_parms = 1;
#endif
case FPGA_LOAD:
case FPGA_LOADP:
case FPGA_LOADB:
case FPGA_LOADBP:
case FPGA_DUMP:
if (!fpga_data || !data_size)
wrong_parms = 1;
break;
#if defined(CONFIG_CMD_FPGA_LOADMK)
case FPGA_LOADMK:
if (!fpga_data)
wrong_parms = 1;
break;
#endif
}
if (wrong_parms) {
puts("Wrong parameters for FPGA request\n");
op = FPGA_NONE;
}
switch (op) {
case FPGA_NONE:
return CMD_RET_USAGE;
case FPGA_INFO:
rc = fpga_info(dev);
break;
case FPGA_LOAD:
rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
break;
#if defined(CONFIG_CMD_FPGA_LOADP)
case FPGA_LOADP:
rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
break;
#endif
case FPGA_LOADB:
rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
break;
#if defined(CONFIG_CMD_FPGA_LOADBP)
case FPGA_LOADBP:
rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
break;
#endif
#if defined(CONFIG_CMD_FPGA_LOADFS)
case FPGA_LOADFS:
rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
break;
#endif
#if defined(CONFIG_CMD_FPGA_LOADMK)
case FPGA_LOADMK:
switch (genimg_get_format(fpga_data)) {
#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
{
image_header_t *hdr =
(image_header_t *)fpga_data;
ulong data;
uint8_t comp;
comp = image_get_comp(hdr);
if (comp == IH_COMP_GZIP) {
#if defined(CONFIG_GZIP)
ulong image_buf = image_get_data(hdr);
data = image_get_load(hdr);
ulong image_size = ~0UL;
if (gunzip((void *)data, ~0UL,
(void *)image_buf,
&image_size) != 0) {
puts("GUNZIP: error\n");
return 1;
}
data_size = image_size;
#else
puts("Gunzip image is not supported\n");
return 1;
#endif
} else {
data = (ulong)image_get_data(hdr);
data_size = image_get_data_size(hdr);
}
rc = fpga_load(dev, (void *)data, data_size,
BIT_FULL);
}
break;
#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
{
const void *fit_hdr = (const void *)fpga_data;
int noffset;
const void *fit_data;
if (fit_uname == NULL) {
puts("No FIT subimage unit name\n");
return 1;
}
if (!fit_check_format(fit_hdr)) {
puts("Bad FIT image format\n");
return 1;
}
/* get fpga component image node offset */
noffset = fit_image_get_node(fit_hdr,
fit_uname);
if (noffset < 0) {
printf("Can't find '%s' FIT subimage\n",
fit_uname);
return 1;
}
/* verify integrity */
if (!fit_image_verify(fit_hdr, noffset)) {
puts ("Bad Data Hash\n");
return 1;
}
/* get fpga subimage data address and length */
if (fit_image_get_data(fit_hdr, noffset,
&fit_data, &data_size)) {
puts("Fpga subimage data not found\n");
return 1;
}
rc = fpga_load(dev, fit_data, data_size,
BIT_FULL);
}
break;
#endif
default:
puts("** Unknown image type\n");
rc = FPGA_FAIL;
break;
}
break;
#endif
case FPGA_DUMP:
rc = fpga_dump(dev, fpga_data, data_size);
break;
default:
printf("Unknown operation\n");
return CMD_RET_USAGE;
}
return rc;
}
/* command form:
* fpga <op> <device number> <data addr> <datasize>
* where op is 'load', 'dump', or 'info'
* If there is no device number field, the fpga environment variable is used.
* If there is no data addr field, the fpgadata environment variable is used.
* The info command requires no data address field.
*/
int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
int op, dev = FPGA_INVALID_DEVICE;
size_t data_size = 0;
void *fpga_data = NULL;
char *devstr = getenv ("fpga");
char *datastr = getenv ("fpgadata");
int rc = FPGA_FAIL;
int wrong_parms = 0;
#if defined (CONFIG_FIT)
const char *fit_uname = NULL;
ulong fit_addr;
#endif
if (devstr)
dev = (int) simple_strtoul (devstr, NULL, 16);
if (datastr)
fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
switch (argc) {
case 5: /* fpga <op> <dev> <data> <datasize> */
data_size = simple_strtoul (argv[4], NULL, 16);
case 4: /* fpga <op> <dev> <data> */
#if defined(CONFIG_FIT)
if (fit_parse_subimage (argv[3], (ulong)fpga_data,
&fit_addr, &fit_uname)) {
fpga_data = (void *)fit_addr;
debug("* fpga: subimage '%s' from FIT image "
"at 0x%08lx\n",
fit_uname, fit_addr);
} else
#endif
{
fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
debug("* fpga: cmdline image address = 0x%08lx\n",
(ulong)fpga_data);
}
debug("%s: fpga_data = 0x%x\n", __func__, (uint) fpga_data);
case 3: /* fpga <op> <dev | data addr> */
dev = (int) simple_strtoul (argv[2], NULL, 16);
debug("%s: device = %d\n", __func__, dev);
/* FIXME - this is a really weak test */
if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
debug("%s: Assuming buffer pointer in arg 3\n",
__func__);
#if defined(CONFIG_FIT)
if (fit_parse_subimage (argv[2], (ulong)fpga_data,
&fit_addr, &fit_uname)) {
fpga_data = (void *)fit_addr;
debug("* fpga: subimage '%s' from FIT image "
"at 0x%08lx\n",
fit_uname, fit_addr);
} else
#endif
{
fpga_data = (void *) dev;
debug("* fpga: cmdline image address = "
"0x%08lx\n", (ulong)fpga_data);
}
debug("%s: fpga_data = 0x%x\n",
__func__, (uint) fpga_data);
dev = FPGA_INVALID_DEVICE; /* reset device num */
}
case 2: /* fpga <op> */
op = (int) fpga_get_op (argv[1]);
break;
default:
debug("%s: Too many or too few args (%d)\n",
__func__, argc);
op = FPGA_NONE; /* force usage display */
break;
}
if (dev == FPGA_INVALID_DEVICE) {
puts("FPGA device not specified\n");
op = FPGA_NONE;
}
switch (op) {
case FPGA_NONE:
case FPGA_INFO:
break;
case FPGA_LOAD:
case FPGA_LOADB:
case FPGA_DUMP:
if (!fpga_data || !data_size)
wrong_parms = 1;
break;
case FPGA_LOADMK:
if (!fpga_data)
wrong_parms = 1;
break;
}
if (wrong_parms) {
puts("Wrong parameters for FPGA request\n");
op = FPGA_NONE;
}
switch (op) {
case FPGA_NONE:
return CMD_RET_USAGE;
case FPGA_INFO:
rc = fpga_info (dev);
break;
case FPGA_LOAD:
rc = fpga_load (dev, fpga_data, data_size);
break;
case FPGA_LOADB:
rc = fpga_loadbitstream(dev, fpga_data, data_size);
break;
case FPGA_LOADMK:
switch (genimg_get_format (fpga_data)) {
case IMAGE_FORMAT_LEGACY:
{
image_header_t *hdr = (image_header_t *)fpga_data;
ulong data;
data = (ulong)image_get_data (hdr);
data_size = image_get_data_size (hdr);
rc = fpga_load (dev, (void *)data, data_size);
}
break;
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
{
const void *fit_hdr = (const void *)fpga_data;
int noffset;
const void *fit_data;
if (fit_uname == NULL) {
puts ("No FIT subimage unit name\n");
return 1;
}
if (!fit_check_format (fit_hdr)) {
puts ("Bad FIT image format\n");
return 1;
}
/* get fpga component image node offset */
noffset = fit_image_get_node (fit_hdr, fit_uname);
if (noffset < 0) {
printf ("Can't find '%s' FIT subimage\n", fit_uname);
return 1;
}
/* verify integrity */
if (!fit_image_verify(fit_hdr, noffset)) {
puts ("Bad Data Hash\n");
return 1;
}
/* get fpga subimage data address and length */
if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
puts ("Could not find fpga subimage data\n");
return 1;
}
rc = fpga_load (dev, fit_data, data_size);
}
break;
#endif
default:
puts ("** Unknown image type\n");
rc = FPGA_FAIL;
break;
}
break;
case FPGA_DUMP:
rc = fpga_dump (dev, fpga_data, data_size);
break;
default:
printf ("Unknown operation\n");
return CMD_RET_USAGE;
}
return (rc);
}
int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype)
{
unsigned int length;
unsigned int swapsize;
unsigned char *dataptr;
unsigned int i;
const fpga_desc *desc;
xilinx_desc *xdesc;
dataptr = (unsigned char *)fpgadata;
/* Find out fpga_description */
desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
/* Assign xilinx device description */
xdesc = desc->devdesc;
/* skip the first bytes of the bitsteam, their meaning is unknown */
length = (*dataptr << 8) + *(dataptr + 1);
dataptr += 2;
dataptr += length;
/* get design name (identifier, length, string) */
length = (*dataptr << 8) + *(dataptr + 1);
dataptr += 2;
if (*dataptr++ != 0x61) {
debug("%s: Design name id not recognized in bitstream\n",
__func__);
return FPGA_FAIL;
}
length = (*dataptr << 8) + *(dataptr + 1);
dataptr += 2;
printf(" design filename = \"%s\"\n", dataptr);
dataptr += length;
/* get part number (identifier, length, string) */
if (*dataptr++ != 0x62) {
printf("%s: Part number id not recognized in bitstream\n",
__func__);
return FPGA_FAIL;
}
length = (*dataptr << 8) + *(dataptr + 1);
dataptr += 2;
if (xdesc->name) {
i = (ulong)strstr((char *)dataptr, xdesc->name);
if (!i) {
printf("%s: Wrong bitstream ID for this device\n",
__func__);
printf("%s: Bitstream ID %s, current device ID %d/%s\n",
__func__, dataptr, devnum, xdesc->name);
return FPGA_FAIL;
}
} else {
printf("%s: Please fill correct device ID to xilinx_desc\n",
__func__);
}
printf(" part number = \"%s\"\n", dataptr);
dataptr += length;
/* get date (identifier, length, string) */
if (*dataptr++ != 0x63) {
printf("%s: Date identifier not recognized in bitstream\n",
__func__);
return FPGA_FAIL;
}
length = (*dataptr << 8) + *(dataptr+1);
dataptr += 2;
printf(" date = \"%s\"\n", dataptr);
dataptr += length;
/* get time (identifier, length, string) */
if (*dataptr++ != 0x64) {
printf("%s: Time identifier not recognized in bitstream\n",
__func__);
return FPGA_FAIL;
}
length = (*dataptr << 8) + *(dataptr+1);
dataptr += 2;
printf(" time = \"%s\"\n", dataptr);
dataptr += length;
/* get fpga data length (identifier, length) */
if (*dataptr++ != 0x65) {
printf("%s: Data length id not recognized in bitstream\n",
__func__);
return FPGA_FAIL;
}
swapsize = ((unsigned int) *dataptr << 24) +
((unsigned int) *(dataptr + 1) << 16) +
((unsigned int) *(dataptr + 2) << 8) +
((unsigned int) *(dataptr + 3));
dataptr += 4;
printf(" bytes in bitstream = %d\n", swapsize);
return fpga_load(devnum, dataptr, swapsize, bstype);
}
