void ft_board_setup(void *blob, bd_t *bd) { do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 4, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", bd->bi_busfreq, 1); fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose); #endif }
void ft_pci_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif }
void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCI2 ft_fsl_pci_setup(blob, "pci1", &pci2_hose); #endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); #endif }
void ft_pci_board_setup(void *blob) { /* According to h/w manual, PCIE2 is at lower address(0x9000) * than PCIE1(0xa000). * Hence PCIE2 is made to occupy the pci1 position in dts to * keep the addresses sorted there. * Generally the case with all FSL SOCs. */ #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); #endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); #endif }
void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); #endif #ifdef CONFIG_PCIE3 ft_fsl_pci_setup(blob, "pci3", &pcie2_hose); #endif #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif }
void ft_board_setup(void *blob, bd_t *bd) { int off; u64 *tmp; u32 *addrcells; ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCI2 ft_fsl_pci_setup(blob, "pci1", &pci2_hose); #endif /* * Warn if it looks like the device tree doesn't match u-boot. * This is just an estimation, based on the location of CCSR, * which is defined by the "reg" property in the soc node. */ off = fdt_path_offset(blob, "/soc8641"); addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); if (tmp) { u64 addr; if (addrcells && (*addrcells == 1)) addr = *(u32 *)tmp; else addr = *tmp; if (addr != CONFIG_SYS_CCSRBAR_PHYS) printf("WARNING: The CCSRBAR address in your .dts " "does not match the address of the CCSR " "in u-boot. This means your .dts might " "be old.\n"); } }
void ft_board_setup(void *blob, bd_t *bd) { #if defined(CONFIG_SYS_UCC_RMII_MODE) int nodeoff, off, err; unsigned int val; const u32 *ph; const u32 *index; /* fixup device tree for supporting rmii mode */ nodeoff = -1; while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff, "ucc_geth")) >= 0) { err = fdt_setprop_string(blob, nodeoff, "tx-clock-name", "clk16"); if (err < 0) { printf("WARNING: could not set tx-clock-name %s.\n", fdt_strerror(err)); break; } err = fdt_setprop_string(blob, nodeoff, "phy-connection-type", "rmii"); if (err < 0) { printf("WARNING: could not set phy-connection-type " "%s.\n", fdt_strerror(err)); break; } index = fdt_getprop(blob, nodeoff, "cell-index", 0); if (index == NULL) { printf("WARNING: could not get cell-index of ucc\n"); break; } ph = fdt_getprop(blob, nodeoff, "phy-handle", 0); if (ph == NULL) { printf("WARNING: could not get phy-handle of ucc\n"); break; } off = fdt_node_offset_by_phandle(blob, *ph); if (off < 0) { printf("WARNING: could not get phy node %s.\n", fdt_strerror(err)); break; } val = 0x7 + *index; /* RMII phy address starts from 0x8 */ err = fdt_setprop(blob, off, "reg", &val, sizeof(u32)); if (err < 0) { printf("WARNING: could not set reg for phy-handle " "%s.\n", fdt_strerror(err)); break; } } #endif ft_cpu_setup(blob, bd); #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif fdt_board_fixup_esdhc(blob, bd); fdt_board_fixup_qe_uart(blob, bd); fdt_board_fixup_qe_usb(blob, bd); }