static int __init plat_enable_iocoherency(void) { int supported = 0; if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; pr_info("Enabled Bonito CPU coherency\n"); supported = 1; } if (strstr(fw_getcmdline(), "iobcuncached")) { BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); pr_info("Disabled Bonito IOBC coherency\n"); } else { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCIMEMBASECFG |= (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); pr_info("Enabled Bonito IOBC coherency\n"); } } else if (gcmp_niocu() != 0) { /* Nothing special needs to be done to enable coherency */ pr_info("CMP IOCU detected\n"); if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); return 0; } supported = 1; } hw_coherentio = supported; return supported; }
static void __init pci_clock_check(void) { unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; static const int pciclocks[] __initconst = { 33, 20, 25, 30, 12, 16, 37, 10 }; int pciclock = pciclocks[jmpr]; char *optptr, *argptr = fw_getcmdline(); /* * If user passed a pci_clock= option, don't tack on another one */ optptr = strstr(argptr, "pci_clock="); if (optptr && (optptr == argptr || optptr[-1] == ' ')) return; if (pciclock != 33) { pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n", pciclock); argptr += strlen(argptr); sprintf(argptr, " pci_clock=%d", pciclock); if (pciclock < 20 || pciclock > 66) pr_warn("WARNING: IDE timing calculations will be " "incorrect\n"); } }
static void __init console_config(void) { char console_string[40]; int baud = 0; char parity = '\0', bits = '\0', flow = '\0'; char *s; s = fw_getenv("modetty0"); if (s) { while (*s >= '0' && *s <= '9') baud = baud*10 + *s++ - '0'; if (*s == ',') s++; if (*s) parity = *s++; if (*s == ',') s++; if (*s) bits = *s++; if (*s == ',') s++; if (*s == 'h') flow = 'r'; } if (baud == 0) baud = 38400; if (parity != 'n' && parity != 'o' && parity != 'e') parity = 'n'; if (bits != '7' && bits != '8') bits = '8'; if (flow == '\0') flow = 'r'; if ((strstr(fw_getcmdline(), "earlycon=")) == NULL) { sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud, parity, bits); setup_early_serial8250_console(console_string); } if ((strstr(fw_getcmdline(), "console=")) == NULL) { sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); strcat(fw_getcmdline(), console_string); pr_info("Config serial console:%s\n", console_string); } }
static char * __init pic32_getcmdline(void) { /* * arch_mem_init() has not been called yet, so we don't have a real * command line setup if using CONFIG_CMDLINE_BOOL. */ #ifdef CONFIG_CMDLINE_OVERRIDE return CONFIG_CMDLINE; #else return fw_getcmdline(); #endif }
static void __init pci_clock_check(void) { unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; static const int pciclocks[] __initconst = { 33, 20, 25, 30, 12, 16, 37, 10 }; int pciclock = pciclocks[jmpr]; char *argptr = fw_getcmdline(); if (pciclock != 33 && !strstr(argptr, "idebus=")) { pr_warn("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock); argptr += strlen(argptr); sprintf(argptr, " idebus=%d", pciclock); if (pciclock < 20 || pciclock > 66) pr_warn("WARNING: IDE timing calculations will be incorrect\n"); } }
static int __init plat_enable_iocoherency(void) { int supported = 0; u32 cfg; if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; pr_info("Enabled Bonito CPU coherency\n"); supported = 1; } if (strstr(fw_getcmdline(), "iobcuncached")) { BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); pr_info("Disabled Bonito IOBC coherency\n"); } else { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCIMEMBASECFG |= (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); pr_info("Enabled Bonito IOBC coherency\n"); } } else if (mips_cps_numiocu(0) != 0) { /* Nothing special needs to be done to enable coherency */ pr_info("CMP IOCU detected\n"); cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) { pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); return 0; } supported = 1; } hw_coherentio = supported; return supported; }