void
main (void)
{
memset (hash1, 0, SMINI_HASH_SIZE); // zero fpga bitstream hash. This forces reload
init_smini ();
set_led_0 (0);
set_led_1 (0);
EA = 0; // disable all interrupts
patch_usb_descriptors();
setup_autovectors ();
usb_install_handlers ();
//hook_timer_tick ((unsigned short) isr_tick);
EIEX4 = 1; // disable INT4 FIXME
EA = 1; // global interrupt enable
fx2_renumerate (); // simulates disconnect / reconnect
main_loop ();
}
void main(void)
{
EA = 0; // disable all interrupts
usb_jtag_init();
eeprom_init();
setup_autovectors ();
usb_install_handlers ();
EA = 1; // enable interrupts
fx2_renumerate(); // simulates disconnect / reconnect
main_loop();
}
void
main (void)
{
init_usrp ();
EA = 0; // disable all interrupts
setup_autovectors ();
usb_install_handlers ();
EIEX4 = 0;
EA = 1; // global interrupt enable
fx2_renumerate (); // simulates disconnect / reconnect
main_loop ();
}
void main(void)
{
CPUCS = bmCLKSPD1;
init_IO();
EA = 0; // disable interrupts
setup_autovectors();
usb_install_handlers();
EA = 1;
fx2_renumerate();
while(1) {
if(usb_setup_packet_avail())
usb_handle_setup_packet();
}
}
void
main (void)
{
#if 0
g_rx_enable = 0; // FIXME (work around initialization bug)
g_tx_enable = 0;
g_rx_overrun = 0;
g_tx_underrun = 0;
#endif
PORTECFG = 0x00;
OEE = 0x0f;
IOE = 0x0c;
memset (hash1, 0, USRP_HASH_SIZE); // zero fpga bitstream hash. This forces reload
patch_usb_descriptors();
init_usrp ();
init_gpif ();
// if (UC_START_WITH_GSTATE_OUTPUT_ENABLED)
// IFCONFIG |= bmGSTATE; // no conflict, start with it on
set_led_0 (0);
set_led_1 (0);
EA = 0; // disable all interrupts
setup_autovectors ();
usb_install_handlers ();
hook_timer_tick ((unsigned short) isr_tick);
EIEX4 = 1; // disable INT4 FIXME
EA = 1; // global interrupt enable
IOE = 0x04;
fx2_renumerate (); // simulates disconnect / reconnect
IOE = 0x08;
main_loop ();
}
unsigned char app_vendor_cmd(void)
{
// OUT requests. Pretend we handle them all...
if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_OUT){
if(bRequest == RQ_GET_STATUS){
Running = 1;
};
return 1;
}
// IN requests.
switch (bRequest){
case 0x90: // Read EEPROM
{ // We need a block for addr
BYTE addr = (wIndexL<<1) & 0x7F;
EP0BUF[0] = eeprom[addr];
EP0BUF[1] = eeprom[addr+1];
EP0BCL = (wLengthL<2) ? wLengthL : 2;
}
break;
case 0x91: // change USB speed
if (wIndexL == 0){ // high speed
CT1 &= ~0x02;
EP0BUF[0] = 0x2;
fx2_renumerate(); // renumerate
}else{ // full speed
CT1 |= 0x02;
EP0BUF[0] = 0x1;
fx2_renumerate(); // renumerate
}
EP0BCH = 0; // Arm endpoint
EP0BCL = 1; // # bytes to transfer
break;
case 0x92: // change JTAG enable
if (wIndexL == 0){ // FX2 is master of JTAG
IOC |= (1 << 7);
}else{ // external connector is master of JTAG
IOC &= ~(1 << 7);
}
EP0BCH = 0; // Arm endpoint
EP0BCL = 0; // # bytes to transfer
break;
case 0x93: // change synchronous/asynchronous mode
if(wIndexL == 0){ // sync
IFCONFIG &= ~bmASYNC;
EP0BUF[0] = 0;
}else{
IFCONFIG |= bmASYNC; // async
EP0BUF[0] = 1;
}
EP0BCH = 0; // Arm endpoint
EP0BCL = 1;
break;
case 0x94: // get Firmware version
{
int i=0;
char* ver=FWVERSION;
while(ver[i]!='\0'){
EP0BUF[i]=ver[i];
i++;
}
EP0BCH = 0; // Arm endpoint
EP0BCL = i;
break;
}
default:
// dummy data
EP0BUF[0] = 0x36;
EP0BUF[1] = 0x83;
EP0BCH = 0;
EP0BCL = (wLengthL<2) ? wLengthL : 2;
}
return 1;
}
void main(void) {
init_usrp();
init_gpif();
// init_se4110(); // MIS - this is no longer required for EK3, 4110 or 4120 varient
init_se4120(); // MIS - initialise SE4120 - default is to Hardware programming mode
// ***********Should first read the port (PA3) to see if S/W programming is allowed. **************
//------------------------------------------- Hardware programming start - just keep separate for now
// Use portA for Hardware programming,
// as can't split PortB at bit level when functionality of PortB is set to GPIF mode / FIFO mode
hard_program_se4120(0x01); // 0x1 : F0 = 0, F1 = 1, F2=0 : select the chosen Sampling /Serial format
//---------------------------------------------Hardware programming end
//-------------------------------------------Software programming start - just keep separate for now
// Just re-program it once, then leave in S/W mode
soft_program_se4120(0xbc, 0x18); // Change to required S/W Prog mode - MSByte first
//--------------------------------------------Software programming end
/*
//------------------------------------------------debug code start
while (1) //DEBUG
{
unsigned short i = 0;
unsigned short j = 0;
for (i = 0x0; i <= 0xff; i += 0x4)
{
soft_program_se4120((0xFD & i), 0x18); // Change to required S/W Prog mode - MSByte first
toggle_portD();
for (j = 0x0; j < 0x08; j++)
{
mdelay(0xff); // 4 ms x delay = 0.5 secs ((clock is still at 12MHz not 48MHz)
}
}
// hold it here ! MIS - else init_usrp will reset FIFO / portb settings.
}
//---------------------------------------------debug code end
*/
EA = 0; // disable all interrupts
setup_autovectors();
usb_install_handlers();
EIEX4 = 1; // disable INT4 FIXME
EA = 1; // global interrupt enable
fx2_renumerate(); // simulates disconnect / reconnect
// enable_se4110(); // MIS - this is no longer required for EK3, 4110 or 4120 varient - leave for EK2 compatibility ?
main_loop();
}
