static int __disable_gpufreq(gckGALDEVICE device)
{
gctUINT32 clockRate = 0;
gceSTATUS status = gcvSTATUS_OK;
int i;
for(i = 0; i < gcdMAX_GPU_COUNT; i++)
{
if(device->kernels[i] != gcvNULL)
{
gckHARDWARE hardware = device->kernels[i]->hardware;
if(!hardware->devObj.kobj)
continue;
gckOS_GPUFreqNotifierCallChain(
device->os,
GPUFREQ_GPU_EVENT_DESTORY,
(gctPOINTER) &hardware->devObj);
}
}
status = gckOS_QueryClkRate(device->os, gcvCORE_MAJOR, &clockRate);
if(gcmIS_SUCCESS(status) && clockRate != 0)
{
gpufreq_exit(device->os);
printk("[galcore] gpufreq exited\n");
}
return 0;
}
static ssize_t show_register_stats (struct device *dev,
struct device_attribute *attr,
char * buf)
{
gckKERNEL kernel = gcvNULL;
gctUINT32 clockControl, clockRate, idle, len = 0, i = 0;
gctBOOL isIdle;
for(; i< gcdMAX_GPU_COUNT; i++)
{
kernel = galDevice->kernels[i];
if(kernel != gcvNULL)
{
if(i == gcvCORE_MAJOR)
{
gcmkVERIFY_OK(gckOS_DirectReadRegister(galDevice->os, gcvCORE_MAJOR, 0x00000, &clockControl));
len += sprintf(buf+len, "clock register: [0x%02x]\n", clockControl);
if(has_feat_gc_shader())
{
gctUINT32 shClkRate;
gcmkVERIFY_OK(gckOS_QueryShClkRate(galDevice->os, &shClkRate));
len += sprintf(buf+len, "shader clock rate: [%d] MHz\n", (gctUINT32)shClkRate/1000/1000);
}
}
len += sprintf(buf+len, "[%s]\n", _core_desc[i]);
gcmkVERIFY_OK(gckHARDWARE_QueryIdleEx(kernel->hardware, &idle, &isIdle));
gcmkVERIFY_OK(gckOS_QueryClkRate(galDevice->os, i, &clockRate));
len += sprintf(buf+len, " idle register: [0x%02x][%s]\n",
idle, (gcvTRUE == isIdle)?"idle":"busy");
len += sprintf(buf+len, " clock rate: [%d] MHz\n", (gctUINT32)clockRate/1000/1000);
}
}
return len +=sprintf(buf+len, "options:\n"
" echo Core 0xAddr > register_stats\n"
" e.g: echo 0 0x664 > register_stats\n"
" # 0 means core 0\n"
" # 0x664 means register address\n");
}
static ssize_t show_current_freq (struct device *dev,
struct device_attribute *attr,
char * buf)
{
gceSTATUS status = gcvSTATUS_OK;
unsigned int clockRate = 0;
int i = 0, len = 0;
for(i = 0; i < gcdMAX_GPU_COUNT; i++)
{
if(galDevice->kernels[i] != gcvNULL)
{
status = gckOS_QueryClkRate(galDevice->os, i, &clockRate);
len += sprintf(buf+len, "[%s] current frequency: %u KHZ\n", _core_desc[i], clockRate/1000);
}
}
return len;
}
static ssize_t show_clk_rate (struct device *dev,
struct device_attribute *attr,
char * buf)
{
gceSTATUS status;
unsigned int clockRate = 0;
int i = 0, len = 0;
for(i = 0; i < gcdMAX_GPU_COUNT; i++)
{
if(galDevice->kernels[i] != gcvNULL)
{
status = gckOS_QueryClkRate(galDevice->os, i, &clockRate);
if(status == gcvSTATUS_OK)
len += sprintf(buf+len, "[%5s] current frequency: %u MHZ\n", _core_desc[i], clockRate/1000/1000);
else
len += sprintf(buf+len, "get clk rate failed, core: %5s", _core_desc[i]);
# if MRVL_CONFIG_SHADER_CLK_CONTROL
if(has_feat_gc_shader() && i == 0)
{
unsigned int shClkRate = 0;
status = gckOS_QueryShClkRate(galDevice->os, &shClkRate);
if(!status)
{
len += sprintf(buf+len, "[%5s] current frequency: %u MHZ\n", "Shader", shClkRate/1000/1000);
}
else
{
len += sprintf(buf+len, "get shader clk rate failed, core: %5s", "Shader");
}
}
# endif
}
}
return len;
}
