void gen6_draw_wm_raster(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */ if ((DIRTY(RASTERIZER) || DIRTY(POLY_STIPPLE)) && vec->rasterizer->state.poly_stipple_enable) { if (ilo_dev_gen(r->dev) == ILO_GEN(6)) gen6_wa_pre_non_pipelined(r); gen6_3DSTATE_POLY_STIPPLE_PATTERN(r->builder, &vec->poly_stipple); gen6_3DSTATE_POLY_STIPPLE_OFFSET(r->builder, 0, 0); } /* 3DSTATE_LINE_STIPPLE */ if (DIRTY(RASTERIZER) && vec->rasterizer->state.line_stipple_enable) { if (ilo_dev_gen(r->dev) == ILO_GEN(6)) gen6_wa_pre_non_pipelined(r); gen6_3DSTATE_LINE_STIPPLE(r->builder, vec->rasterizer->state.line_stipple_pattern, vec->rasterizer->state.line_stipple_factor + 1); } /* 3DSTATE_AA_LINE_PARAMETERS */ if (DIRTY(RASTERIZER) && vec->rasterizer->state.line_smooth) { if (ilo_dev_gen(r->dev) == ILO_GEN(6)) gen6_wa_pre_non_pipelined(r); gen6_3DSTATE_AA_LINE_PARAMETERS(r->builder); } }
static void gen6_draw_gs_svbi(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { const bool emit = gen6_draw_update_max_svbi(r, vec, session); /* 3DSTATE_GS_SVB_INDEX */ if (emit) { if (ilo_dev_gen(r->dev) == ILO_GEN(6)) gen6_wa_pre_non_pipelined(r); gen6_3DSTATE_GS_SVB_INDEX(r->builder, 0, 0, r->state.so_max_vertices, false); if (r->hw_ctx_changed) { int i; /* * From the Sandy Bridge PRM, volume 2 part 1, page 148: * * "If a buffer is not enabled then the SVBI must be set to 0x0 * in order to not cause overflow in that SVBI." * * "If a buffer is not enabled then the MaxSVBI must be set to * 0xFFFFFFFF in order to not cause overflow in that SVBI." */ for (i = 1; i < 4; i++) { gen6_3DSTATE_GS_SVB_INDEX(r->builder, i, 0, 0xffffffff, false); } } } }
static void gen6_draw_wm_multisample(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */ if (DIRTY(SAMPLE_MASK) || DIRTY(FB)) { const uint32_t *packed_sample_pos; packed_sample_pos = (vec->fb.num_samples > 1) ? &r->packed_sample_position_4x : &r->packed_sample_position_1x; if (ilo_dev_gen(r->dev) == ILO_GEN(6)) { gen6_wa_pre_non_pipelined(r); gen6_wa_pre_3dstate_multisample(r); } gen6_3DSTATE_MULTISAMPLE(r->builder, vec->fb.num_samples, packed_sample_pos, vec->rasterizer->state.half_pixel_center); gen6_3DSTATE_SAMPLE_MASK(r->builder, (vec->fb.num_samples > 1) ? vec->sample_mask : 0x1); } }
void gen6_draw_vs(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { const bool emit_3dstate_vs = (DIRTY(VS) || r->instruction_bo_changed); const bool emit_3dstate_constant_vs = session->pcb_vs_changed; /* * the classic i965 does this in upload_vs_state(), citing a spec that I * cannot find */ if (emit_3dstate_vs && ilo_dev_gen(r->dev) == ILO_GEN(6)) gen6_wa_pre_non_pipelined(r); /* 3DSTATE_CONSTANT_VS */ if (emit_3dstate_constant_vs) { gen6_3DSTATE_CONSTANT_VS(r->builder, &r->state.vs.PUSH_CONSTANT_BUFFER, &r->state.vs.PUSH_CONSTANT_BUFFER_size, 1); } /* 3DSTATE_VS */ if (emit_3dstate_vs) gen6_3DSTATE_VS(r->builder, vec->vs); if (emit_3dstate_constant_vs && ilo_dev_gen(r->dev) == ILO_GEN(6)) gen6_wa_post_3dstate_constant_vs(r); }
void gen6_draw_common_base_address(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { /* STATE_BASE_ADDRESS */ if (r->state_bo_changed || r->instruction_bo_changed || r->batch_bo_changed) { if (ilo_dev_gen(r->dev) == ILO_GEN(6)) gen6_wa_pre_non_pipelined(r); if (ilo_dev_gen(r->dev) >= ILO_GEN(8)) gen8_state_base_address(r->builder, r->hw_ctx_changed); else gen6_state_base_address(r->builder, r->hw_ctx_changed); /* * From the Sandy Bridge PRM, volume 1 part 1, page 28: * * "The following commands must be reissued following any change to * the base addresses: * * * 3DSTATE_BINDING_TABLE_POINTERS * * 3DSTATE_SAMPLER_STATE_POINTERS * * 3DSTATE_VIEWPORT_STATE_POINTERS * * 3DSTATE_CC_POINTERS * * MEDIA_STATE_POINTERS" * * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is * reasonable to also reissue the command. Same to PCB. */ session->viewport_changed = true; session->scissor_changed = true; session->blend_changed = true; session->dsa_changed = true; session->cc_changed = true; session->sampler_vs_changed = true; session->sampler_gs_changed = true; session->sampler_fs_changed = true; session->pcb_vs_changed = true; session->pcb_gs_changed = true; session->pcb_fs_changed = true; session->binding_table_vs_changed = true; session->binding_table_gs_changed = true; session->binding_table_fs_changed = true; } }
void gen6_draw_common_sip(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { /* STATE_SIP */ if (r->hw_ctx_changed) { if (ilo_dev_gen(r->dev) == ILO_GEN(6)) gen6_wa_pre_non_pipelined(r); gen6_STATE_SIP(r->builder, 0); } }
void gen6_draw_common_select(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { /* PIPELINE_SELECT */ if (r->hw_ctx_changed) { if (ilo_dev_gen(r->dev) == ILO_GEN(6)) gen6_wa_pre_non_pipelined(r); gen6_PIPELINE_SELECT(r->builder, 0x0); } }
void ilo_render_emit_rectlist_commands_gen6(struct ilo_render *r, const struct ilo_blitter *blitter, const struct ilo_render_rectlist_session *session) { ILO_DEV_ASSERT(r->dev, 6, 6); gen6_wa_pre_non_pipelined(r); gen6_rectlist_wm_multisample(r, blitter); gen6_state_base_address(r->builder, true); gen6_user_3DSTATE_VERTEX_BUFFERS(r->builder, session->vb_start, session->vb_end, sizeof(blitter->vertices[0])); gen6_3DSTATE_VERTEX_ELEMENTS(r->builder, &blitter->ve); gen6_3DSTATE_URB(r->builder, r->dev->urb_size, 0, (blitter->ve.count + blitter->ve.prepend_nosrc_cso) * 4 * sizeof(float), 0); /* 3DSTATE_URB workaround */ if (r->state.gs.active) { ilo_render_emit_flush(r); r->state.gs.active = false; } if (blitter->uses & (ILO_BLITTER_USE_DSA | ILO_BLITTER_USE_CC)) { gen6_3DSTATE_CC_STATE_POINTERS(r->builder, 0, r->state.DEPTH_STENCIL_STATE, r->state.COLOR_CALC_STATE); } gen6_rectlist_vs_to_sf(r, blitter); gen6_rectlist_wm(r, blitter); if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) { gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r->builder, 0, 0, r->state.CC_VIEWPORT); } gen6_rectlist_wm_depth(r, blitter); gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0, blitter->fb.width, blitter->fb.height); gen6_3DPRIMITIVE(r->builder, &blitter->draw, NULL); }
void gen6_draw_sf_rect(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { /* 3DSTATE_DRAWING_RECTANGLE */ if (DIRTY(FB)) { if (ilo_dev_gen(r->dev) == ILO_GEN(6)) gen6_wa_pre_non_pipelined(r); gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0, vec->fb.state.width, vec->fb.state.height); } }
static void gen6_draw_wm_depth(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */ if (DIRTY(FB) || r->batch_bo_changed) { const struct ilo_zs_surface *zs; uint32_t clear_params; if (vec->fb.state.zsbuf) { const struct ilo_surface_cso *surface = (const struct ilo_surface_cso *) vec->fb.state.zsbuf; const struct ilo_texture_slice *slice = ilo_texture_get_slice(ilo_texture(surface->base.texture), surface->base.u.tex.level, surface->base.u.tex.first_layer); assert(!surface->is_rt); zs = &surface->u.zs; clear_params = slice->clear_value; } else { zs = &vec->fb.null_zs; clear_params = 0; } if (ilo_dev_gen(r->dev) == ILO_GEN(6)) { gen6_wa_pre_non_pipelined(r); gen6_wa_pre_depth(r); } gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs, false); gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs); gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs); gen6_3DSTATE_CLEAR_PARAMS(r->builder, clear_params); } }