void
gen8_vec4_generator::generate_code(exec_list *instructions,
struct annotation_info *annotation)
{
if (unlikely(debug_flag)) {
if (shader_prog) {
fprintf(stderr, "Native code for %s vertex shader %d:\n",
shader_prog->Label ? shader_prog->Label : "unnamed",
shader_prog->Name);
} else {
fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
}
}
cfg_t *cfg = NULL;
if (unlikely(debug_flag))
cfg = new(mem_ctx) cfg_t(instructions);
foreach_list(node, instructions) {
vec4_instruction *ir = (vec4_instruction *) node;
struct brw_reg src[3], dst;
if (unlikely(debug_flag))
annotate(brw, annotation, cfg, ir, next_inst_offset);
for (unsigned int i = 0; i < 3; i++) {
src[i] = ir->get_src(prog_data, i);
}
dst = ir->get_dst();
default_state.conditional_mod = ir->conditional_mod;
default_state.predicate = ir->predicate;
default_state.predicate_inverse = ir->predicate_inverse;
default_state.saturate = ir->saturate;
const unsigned pre_emit_nr_inst = nr_inst;
generate_vec4_instruction(ir, dst, src);
if (ir->no_dd_clear || ir->no_dd_check) {
assert(nr_inst == pre_emit_nr_inst + 1 ||
!"no_dd_check or no_dd_clear set for IR emitting more "
"than 1 instruction");
gen8_instruction *last = &store[pre_emit_nr_inst];
gen8_set_no_dd_clear(last, ir->no_dd_clear);
gen8_set_no_dd_check(last, ir->no_dd_check);
}
}
void
vec4_generator::generate_code(exec_list *instructions)
{
int last_native_insn_offset = 0;
const char *last_annotation_string = NULL;
const void *last_annotation_ir = NULL;
if (unlikely(debug_flag)) {
if (shader_prog) {
fprintf(stderr, "Native code for %s vertex shader %d:\n",
shader_prog->Label ? shader_prog->Label : "unnamed",
shader_prog->Name);
} else {
fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
}
}
foreach_list(node, instructions) {
vec4_instruction *inst = (vec4_instruction *)node;
struct brw_reg src[3], dst;
if (unlikely(debug_flag)) {
if (last_annotation_ir != inst->ir) {
last_annotation_ir = inst->ir;
if (last_annotation_ir) {
fprintf(stderr, " ");
if (shader_prog) {
((ir_instruction *) last_annotation_ir)->fprint(stderr);
} else {
const prog_instruction *vpi;
vpi = (const prog_instruction *) inst->ir;
fprintf(stderr, "%d: ", (int)(vpi - prog->Instructions));
_mesa_fprint_instruction_opt(stderr, vpi, 0,
PROG_PRINT_DEBUG, NULL);
}
fprintf(stderr, "\n");
}
}
if (last_annotation_string != inst->annotation) {
last_annotation_string = inst->annotation;
if (last_annotation_string)
fprintf(stderr, " %s\n", last_annotation_string);
}
}
for (unsigned int i = 0; i < 3; i++) {
src[i] = inst->get_src(this->prog_data, i);
}
dst = inst->get_dst();
brw_set_conditionalmod(p, inst->conditional_mod);
brw_set_predicate_control(p, inst->predicate);
brw_set_predicate_inverse(p, inst->predicate_inverse);
brw_set_saturate(p, inst->saturate);
brw_set_mask_control(p, inst->force_writemask_all);
unsigned pre_emit_nr_insn = p->nr_insn;
generate_vec4_instruction(inst, dst, src);
if (inst->no_dd_clear || inst->no_dd_check) {
assert(p->nr_insn == pre_emit_nr_insn + 1 ||
!"no_dd_check or no_dd_clear set for IR emitting more "
"than 1 instruction");
struct brw_instruction *last = &p->store[pre_emit_nr_insn];
if (inst->no_dd_clear)
last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
if (inst->no_dd_check)
last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
}
if (unlikely(debug_flag)) {
brw_dump_compile(p, stderr,
last_native_insn_offset, p->next_insn_offset);
}
last_native_insn_offset = p->next_insn_offset;
}
void
vec4_generator::generate_code(const cfg_t *cfg)
{
struct annotation_info annotation;
memset(&annotation, 0, sizeof(annotation));
foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
struct brw_reg src[3], dst;
if (unlikely(debug_flag))
annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
for (unsigned int i = 0; i < 3; i++) {
src[i] = inst->get_src(this->prog_data, i);
}
dst = inst->get_dst();
brw_set_default_predicate_control(p, inst->predicate);
brw_set_default_predicate_inverse(p, inst->predicate_inverse);
brw_set_default_saturate(p, inst->saturate);
brw_set_default_mask_control(p, inst->force_writemask_all);
brw_set_default_acc_write_control(p, inst->writes_accumulator);
unsigned pre_emit_nr_insn = p->nr_insn;
generate_vec4_instruction(inst, dst, src);
if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
assert(p->nr_insn == pre_emit_nr_insn + 1 ||
!"conditional_mod, no_dd_check, or no_dd_clear set for IR "
"emitting more than 1 instruction");
brw_inst *last = &p->store[pre_emit_nr_insn];
brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
}
}
brw_set_uip_jip(p);
annotation_finalize(&annotation, p->next_insn_offset);
int before_size = p->next_insn_offset;
brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
int after_size = p->next_insn_offset;
if (unlikely(debug_flag)) {
if (shader_prog) {
fprintf(stderr, "Native code for %s vertex shader %d:\n",
shader_prog->Label ? shader_prog->Label : "unnamed",
shader_prog->Name);
} else {
fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
}
fprintf(stderr, "vec4 shader: %d instructions. Compacted %d to %d"
" bytes (%.0f%%)\n",
before_size / 16, before_size, after_size,
100.0f * (before_size - after_size) / before_size);
dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
ralloc_free(annotation.ann);
}
}
void
gen8_vec4_generator::generate_code(exec_list *instructions)
{
int last_native_inst_offset = 0;
const char *last_annotation_string = NULL;
const void *last_annotation_ir = NULL;
if (unlikely(debug_flag)) {
if (shader_prog) {
printf("Native code for vertex shader %d:\n", shader_prog->Name);
} else {
printf("Native code for vertex program %d:\n", prog->Id);
}
}
foreach_list(node, instructions) {
vec4_instruction *ir = (vec4_instruction *) node;
struct brw_reg src[3], dst;
if (unlikely(debug_flag)) {
if (last_annotation_ir != ir->ir) {
last_annotation_ir = ir->ir;
if (last_annotation_ir) {
printf(" ");
if (shader_prog) {
((ir_instruction *) last_annotation_ir)->print();
} else {
const prog_instruction *vpi;
vpi = (const prog_instruction *) ir->ir;
printf("%d: ", (int)(vpi - prog->Instructions));
_mesa_fprint_instruction_opt(stdout, vpi, 0,
PROG_PRINT_DEBUG, NULL);
}
printf("\n");
}
}
if (last_annotation_string != ir->annotation) {
last_annotation_string = ir->annotation;
if (last_annotation_string)
printf(" %s\n", last_annotation_string);
}
}
for (unsigned int i = 0; i < 3; i++) {
src[i] = ir->get_src(prog_data, i);
}
dst = ir->get_dst();
default_state.conditional_mod = ir->conditional_mod;
default_state.predicate = ir->predicate;
default_state.predicate_inverse = ir->predicate_inverse;
default_state.saturate = ir->saturate;
const unsigned pre_emit_nr_inst = nr_inst;
generate_vec4_instruction(ir, dst, src);
if (ir->no_dd_clear || ir->no_dd_check) {
assert(nr_inst == pre_emit_nr_inst + 1 ||
!"no_dd_check or no_dd_clear set for IR emitting more "
"than 1 instruction");
gen8_instruction *last = &store[pre_emit_nr_inst];
gen8_set_no_dd_clear(last, ir->no_dd_clear);
gen8_set_no_dd_check(last, ir->no_dd_check);
}
if (unlikely(debug_flag)) {
disassemble(stdout, last_native_inst_offset, next_inst_offset);
}
last_native_inst_offset = next_inst_offset;
}
