// this task is the initial task running, started by main(). It begins the system tick timer
// and creates all the other task. Then it deletes itself.
void StartupTask(void* pdata)
{
INT8U err;
DEBUGMSG(1,("StartupTask: begin\n\r"));
DEBUGMSG(1,("StartupTask: tick timer\n\r"));
// Initialize BSP functions
BSP_Init();
// re-init the UART so we can use the serial port
initUART0(38400, UART_8N1, UART_FIFO_OFF, getFcclk());
// initialize the driver sub-system
err = OSDRV_SubsysInit(DriverTable, DRIVER_COUNT);
if (err != OS_DRV_NO_ERR) {
RETAILMSG(1,("StartupTask: Failed to initialize driver subsystem: %d\n\r", err));
//park here
while(TRUE);
}
SemPrint = OSSemCreate(1);
// create the the test tasks
// we have OS_STK_GROWTH set to 1, so the stack grows from high to low
DEBUGMSG(1,("StartupTask: Creating the tasks...\n\r"));
OSTaskCreate(PlayTask, (void*)0, (void*)&TaskPlayStk[APP_TASK_DEFAULT_STK_SIZE-1], APP_TASK_PLAY_PRIO);
#ifdef OS_TASK_STAT_EN
//create a CPU monitor task
OSStatInit ();
//?? OSTaskCreate(MonTask, (void*)0, (void*)&TaskMonStk[APP_TASK_DEFAULT_STK_SIZE-1], APP_TASK_MON_PRIO);
#endif //OS_TASK_STAT_EN
// delete ourselves, letting the work be done in the new tasks.
DEBUGMSG(1,("StartupTask: deleting self\n\r"));
OSTaskDel(OS_PRIO_SELF);
}
/*
SpiSetClock - set the SPI master clock
*/
static void SpiSetClock(PSPI_DEVICE pDevice, INT32U ClockRate)
{
//assumes SPI PCLK set to divide by 1
INT32U clk = ((getFcclk()) / ClockRate);
clk = (clk < 2) ? 2 : clk;
WRITEREG8(pDevice->pSSPnCPSR, (clk & 0xFE));
pDevice->Clock = ClockRate;
}
/* Configure Timer1 to generate an interrupt 100 times a second */
void initTimer1(uint32_t cclk)
{
uint32_t prescale;
uint8_t pclk_div;
uint8_t pclk_sel;
uint32_t fcclk;
uint32_t frequency;
/* Call installVector to install ISR before enabling interrupt source. */
installVector(VIC_CH5_TIMER1, &timer1ISR, 0, VIC_VECT_PRIORITY_HIGHEST);
/* find out pclk divider */
pclk_sel = GET_PCLK_SEL( P_SCB_REGS->PCLKSEL0 , PCLK_TIMER1 );
pclk_div = ( pclk_sel == 0 ? 4 : \
pclk_sel == 1 ? 1 : \
pclk_sel == 2 ? 2 : \
pclk_sel == 3 ? 8 : \
0 ); /* this evaluation should never happen */
if( pclk_div == 0 )
{
return;
}
/* Determine prescale amount */
/* Get the frequency of cclk */
fcclk = getFcclk();
/* Determine prescale amount for desired timer frequency */
/* Get Timer1's Prescale Register */
prescale = (fcclk / TMR_FREQ / PR_MATCH);
if( prescale == 0 )
{
return;
}
frequency = (fcclk/pclk_div/prescale);
RETAILMSG(1, ("Timer 1 Frequency: %lu (calculated)\n\r", frequency));
/* Program the Timer registers.
* make sure we are not running at half the speed due to the way the
* counters increment and match */
/* 1. Disable and reset counter */
/* 2. Timer Mode: every rising PCLK edge */
/* 3. Prescale down on the front end to save a little power (prescale - 1) */
/* 4. Reset any interrupt flags */
/* 5. When TC is match value (match - 1), the value programmed to this register must be greater than zero */
/* 6. Interrupt on MR0, Reset on MR0 */
P_TIMER1_REGS->TCR = 0x02; /* disable and reset counter */
P_TIMER1_REGS->CTCR = 0x00; /* Timer Mode: every rising PCLK edge */
P_TIMER1_REGS->PR = prescale - 1; /* prescale down on the front end to save a little power */
P_TIMER1_REGS->IR = 0x3F; /* reset any interrupt flags */
P_TIMER1_REGS->MR0 = PR_MATCH - 1; /* match on TC = 1 */
P_TIMER1_REGS->MCR = MCR_MR0I | MCR_MR0R; /* interrupt on MR0 and reset on MR0; TC will reset */
return;
}
// configure timer2 to free run
void initTimer2(uint32_t cclk)
{
uint8_t pclk_div;
uint8_t pclk_sel;
uint32_t fcclk;
P_SCB_REGS->PCONP |= PCONP_PCTIM2; // enable power on to the timer
// find out pclk divider
pclk_sel = GET_PCLK_SEL( P_SCB_REGS->PCLKSEL1 , PCLK_TIMER2 );
pclk_div = ( pclk_sel == 0 ? 4 : \
pclk_sel == 1 ? 1 : \
pclk_sel == 2 ? 2 : \
pclk_sel == 3 ? 8 : \
0 ); // this evaluation should never happen
if( pclk_div == 0 )
{
return;
}
fcclk = getFcclk(); // get the main clock frequency
timer2Freq = (fcclk/pclk_div); // calculate peripheral clock frequency
// program the timer registers
P_TIMER2_REGS->TCR = 0x02; // disable and reset counter
P_TIMER2_REGS->TCR = 0x00; // clear the reset bit
P_TIMER2_REGS->CTCR = 0x00; // Timer Mode: every rising PCLK edge
P_TIMER2_REGS->PR = 0x00; // no prescale
P_TIMER2_REGS->IR = 0x3F; // reset any interrupt flags
P_TIMER2_REGS->MR0 = 0x00; // no match, run continuously
P_TIMER2_REGS->MCR = 0x00; // no interrupt, run continuously
P_TIMER2_REGS->CCR = 0x00; // no capture
P_TIMER2_REGS->EMR = 0x00; // no external match
return;
}
