int interrupt_init (void)
{
int i;
/* setup GP Timer 1 */
TCTL1 = TCTL_SWR;
for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
reset_timer_masked();
return (0);
}
int timer_init (void)
{
int i;
/* setup GP Timer 1 */
TCTL1 = TCTL_SWR;
for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
/* Reset the timer */
TCTL1 &= ~TCTL_TEN;
TCTL1 |= TCTL_TEN; /* Enable timer */
return (0);
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
unsigned int ufcr_rfdiv;
unsigned int refclk;
#ifdef CONFIG_IMX_SERIAL1
imx_gpio_mode(PC11_PF_UART1_TXD);
imx_gpio_mode(PC12_PF_UART1_RXD);
#else
imx_gpio_mode(PB30_PF_UART2_TXD);
imx_gpio_mode(PB31_PF_UART2_RXD);
#endif
/* Disable UART */
base->ucr1 &= ~UCR1_UARTEN;
/* Set to default POR state */
base->ucr1 = 0x00000004;
base->ucr2 = 0x00000000;
base->ucr3 = 0x00000000;
base->ucr4 = 0x00008040;
base->uesc = 0x0000002B;
base->utim = 0x00000000;
base->ubir = 0x00000000;
base->ubmr = 0x00000000;
base->uts = 0x00000000;
/* Set clocks */
base->ucr4 |= UCR4_REF16;
/* Configure FIFOs */
base->ufcr = 0xa81;
/* set the baud rate.
*
* baud * 16 x
* --------- = -
* refclk y
*
* x - 1 = UBIR
* y - 1 = UBMR
*
* each register is 16 bits wide. refclk max is 96 MHz
*
*/
ufcr_rfdiv = ((base->ufcr) & UFCR_RFDIV) >> 7;
if (ufcr_rfdiv == 6)
ufcr_rfdiv = 7;
else
ufcr_rfdiv = 6 - ufcr_rfdiv;
refclk = get_PERCLK1();
refclk /= ufcr_rfdiv;
/* Set the numerator value minus one of the BRM ratio */
base->ubir = (gd->baudrate / 100) - 1;
/* Set the denominator value minus one of the BRM ratio */
base->ubmr = (refclk/(16 * 100)) - 1;
/* Set to 8N1 */
base->ucr2 &= ~UCR2_PREN;
base->ucr2 |= UCR2_WS;
base->ucr2 &= ~UCR2_STPB;
/* Ignore RTS */
base->ucr2 |= UCR2_IRTS;
/* Enable UART */
base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN;
/* Enable FIFOs */
base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN;
/* Clear status flags */
base->usr2 |= USR2_ADET |
USR2_DTRF |
USR2_IDLE |
USR2_IRINT |
USR2_WAKE |
USR2_RTSF |
USR2_BRCD |
USR2_ORE;
/* Clear status flags */
base->usr1 |= USR1_PARITYERR |
USR1_RTSD |
USR1_ESCF |
USR1_FRAMERR |
USR1_AIRINT |
USR1_AWAKE;
return (0);
}
