int
picos_to_clk(int picos)
{
int clks;
clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
clks++;
}
return clks;
}
void diu_set_pixel_clock(unsigned int pixclock)
{
unsigned long speed_ccb, temp;
u32 pixval;
int ret = 0;
speed_ccb = get_bus_freq(0);
temp = 1000000000 / pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
/* Program HDMI encoder */
/* Switch channel to DIU */
select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
/* Set dispaly encoder */
ret = diu_set_dvi_encoder(temp);
if (ret) {
puts("Failed to set DVI encoder\n");
return;
}
/* Switch channel to default */
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
/* Program pixel clock */
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
((pixval << PXCK_BITS_START) & PXCK_MASK));
/* enable clock*/
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
((pixval << PXCK_BITS_START) & PXCK_MASK));
}
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
phys_size_t initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
defined(CONFIG_NAND_SPL)
ulong speed = get_bus_freq(0);
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
mtsdram(DDR0_01, 0x01000000);
mtsdram(DDR0_03, 0x02030602);
mtsdram(DDR0_04, 0x0A020200);
mtsdram(DDR0_05, 0x02020308);
mtsdram(DDR0_06, 0x0102C812);
mtsdram(DDR0_07, 0x000D0100);
mtsdram(DDR0_08, 0x02430001);
mtsdram(DDR0_09, 0x00011D5F);
mtsdram(DDR0_10, 0x00000100);
mtsdram(DDR0_11, 0x0027C800);
mtsdram(DDR0_12, 0x00000003);
mtsdram(DDR0_14, 0x00000000);
mtsdram(DDR0_17, 0x19000000);
mtsdram(DDR0_18, 0x19191919);
mtsdram(DDR0_19, 0x19191919);
mtsdram(DDR0_20, 0x0B0B0B0B);
mtsdram(DDR0_21, 0x0B0B0B0B);
mtsdram(DDR0_22, 0x00267F0B);
mtsdram(DDR0_23, 0x00000000);
mtsdram(DDR0_24, 0x01010002);
if (speed > 133333334)
mtsdram(DDR0_26, 0x5B26050C);
else
mtsdram(DDR0_26, 0x5B260408);
mtsdram(DDR0_27, 0x0000682B);
mtsdram(DDR0_28, 0x00000000);
mtsdram(DDR0_31, 0x00000000);
mtsdram(DDR0_42, 0x01000006);
mtsdram(DDR0_43, 0x030A0200);
mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001);
denali_wait_for_dlllock();
#endif /* #ifndef CONFIG_NAND_U_BOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+
* Perform data eye search if requested.
* ----------------------------------------------------------*/
denali_core_search_data_eye();
#endif
/*
* Clear possible errors resulting from data-eye-search.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
set_mcsr(get_mcsr());
return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
long int initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_NAND_SPL)
ulong speed = get_bus_freq(0);
#else
ulong speed = 133333333; /* 133MHz is on the safe side */
#endif
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
mtsdram(DDR0_01, 0x01000000);
mtsdram(DDR0_03, 0x02030602);
mtsdram(DDR0_04, 0x0A020200);
mtsdram(DDR0_05, 0x02020308);
mtsdram(DDR0_06, 0x0102C812);
mtsdram(DDR0_07, 0x000D0100);
mtsdram(DDR0_08, 0x02430001);
mtsdram(DDR0_09, 0x00011D5F);
mtsdram(DDR0_10, 0x00000300);
mtsdram(DDR0_11, 0x0027C800);
mtsdram(DDR0_12, 0x00000003);
mtsdram(DDR0_14, 0x00000000);
mtsdram(DDR0_17, 0x19000000);
mtsdram(DDR0_18, 0x19191919);
mtsdram(DDR0_19, 0x19191919);
mtsdram(DDR0_20, 0x0B0B0B0B);
mtsdram(DDR0_21, 0x0B0B0B0B);
mtsdram(DDR0_22, 0x00267F0B);
mtsdram(DDR0_23, 0x00000000);
mtsdram(DDR0_24, 0x01010002);
if (speed > 133333334)
mtsdram(DDR0_26, 0x5B26050C);
else
mtsdram(DDR0_26, 0x5B260408);
mtsdram(DDR0_27, 0x0000682B);
mtsdram(DDR0_28, 0x00000000);
mtsdram(DDR0_31, 0x00000000);
mtsdram(DDR0_42, 0x01000006);
mtsdram(DDR0_43, 0x030A0200);
mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001);
wait_for_dlllock();
#endif /* #ifndef CONFIG_NAND_U_BOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+
* Perform data eye search if requested.
* ----------------------------------------------------------*/
denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
#endif
return (CFG_MBYTES_SDRAM << 20);
}
void sdram_init(void)
{
ulong sdtr1;
ulong rtr;
int i;
/*
* Support for 100MHz and 133MHz SDRAM
*/
if (get_bus_freq(0) > 100000000) {
/*
* 133 MHz SDRAM
*/
sdtr1 = 0x01074015;
rtr = 0x07f00000;
} else {
/*
* default: 100 MHz SDRAM
*/
sdtr1 = 0x0086400d;
rtr = 0x05f00000;
}
for (i=0; i<N_MB0CF; i++) {
/*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
mtsdram0(mem_mb0cf, mb0cf[i].reg);
mtsdram0(mem_sdtr1, sdtr1);
mtsdram0(mem_rtr, rtr);
udelay(200);
/*
* Set memory controller options reg, MCOPT1.
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
mtsdram0(mem_mcopt1, 0x80800000);
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
/*
* OK, size detected -> all done
*/
return;
}
}
}
int checkboard(void)
{
ulong busfreq = get_bus_freq(0);
char buf[32];
puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n");
printf("Built: %s at %s\n", __DATE__ , __TIME__ );
/* printf("MPLD: Revision %d\n", SYS_REVID_GET()); */
printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
return 0;
}
/*
* Autodetect onboard SDRAM on 405 platforms
*/
void sdram_init(void)
{
ulong speed;
ulong sdtr1;
int i;
/*
* Determine SDRAM speed
*/
speed = get_bus_freq(0); /* parameter not used on ppc4xx */
/*
* sdtr1 (register SDRAM0_TR) must take into account timings listed
* in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
* account actual SDRAM size. So we can set up sdtr1 according to what
* is specified in board configuration file while rtr dependds on SDRAM
* size we are assuming before detection.
*/
sdtr1 = compute_sdtr1(speed);
for (i=0; i<N_MB0CF; i++) {
/*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
mtsdram0(mem_mb0cf, mb0cf[i].reg);
mtsdram0(mem_sdtr1, sdtr1);
mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200);
/*
* Set memory controller options reg, MCOPT1.
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
mtsdram0(mem_mcopt1, 0x80800000);
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
/*
* OK, size detected -> all done
*/
return;
}
}
}
void board_add_ram_info(int use_default)
{
u32 val;
printf(" (ECC");
if (!is_ecc_enabled()) {
printf(" not");
}
printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000);
mfsdram(DDR0_03, val);
printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
}
static unsigned long get_internval_val_mhz(void)
{
char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
/*
* interval is the number of platform cycles(MHz) between
* wake up events generated by EPU.
*/
ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
if (interval)
interval_mhz = simple_strtoul(interval, NULL, 10);
return interval_mhz;
}
int checkboard(void)
{
/*
char revision = BOARD_REV;
*/
ulong busfreq = get_bus_freq(0);
char buf[32];
puts ("CPC45 ");
/*
printf("Revision %d ", revision);
*/
printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
return 0;
}
void diu_set_pixel_clock(unsigned int pixclock)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
unsigned long speed_ccb, temp;
u32 pixval;
speed_ccb = get_bus_freq(0);
temp = 1000000000 / pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
debug("DIU pixval = %u\n", pixval);
/* Modify PXCLK in GUTS CLKDVDR */
temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
out_be32(&gur->clkdvdr, temp); /* turn off clock */
out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
}
int interrupt_init_cpu (unsigned *decrementer_count)
{
*decrementer_count = (get_bus_freq (0) / 4) / CONFIG_SYS_HZ;
/*
* It's all broken at the moment and I currently don't need
* interrupts. If you want to fix it, have a look at the epic
* drivers in dink32 v12. They do everthing and Motorola said
* I could use the dink source in this project as long as
* copyright notices remain intact.
*/
epicInit (EPIC_DIRECT_IRQ, 0);
/* EPIC won't generate INT unless Current Task Pri < 15 */
epicCurTaskPrioSet(0);
return (0);
}
void diu_set_pixel_clock(unsigned int pixclock)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile clk512x_t *clk = &immap->clk;
volatile unsigned int *clkdvdr = &clk->scfr[0];
unsigned long speed_ccb, temp, pixval;
speed_ccb = get_bus_freq(0) * 4;
temp = 1000000000/pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
debug("DIU pixval = %lu\n", pixval);
/* Modify PXCLK in GUTS CLKDVDR */
debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
temp = *clkdvdr & 0xFFFFFF00;
*clkdvdr = temp | (pixval & 0xFF);
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
}
void diu_set_pixel_clock(unsigned int pixclock)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
unsigned long speed_ccb, temp, pixval;
speed_ccb = get_bus_freq(0);
temp = 1000000000/pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
debug("DIU pixval = %lu\n", pixval);
/* Modify PXCLK in GUTS CLKDVDR */
debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
temp = *guts_clkdvdr & 0x2000FFFF;
*guts_clkdvdr = temp; /* turn off clock */
*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
}
static unsigned int
picos_to_clk(unsigned int picos)
{
/* use unsigned long long to avoid rounding errors */
const unsigned long long ULL_2e12 = 2000000000000ULL;
unsigned long long clks;
unsigned long long clks_temp;
if (! picos)
return 0;
clks = get_bus_freq(0) * (unsigned long long) picos;
clks_temp = clks;
clks = clks / ULL_2e12;
if (clks_temp % ULL_2e12) {
clks++;
}
if (clks > 0xFFFFFFFFULL) {
clks = 0xFFFFFFFFULL;
}
return (unsigned int) clks;
}
void diu_set_pixel_clock(unsigned int pixclock)
{
unsigned long speed_ccb, temp;
u32 pixval;
int ret = 0;
speed_ccb = get_bus_freq(0);
temp = 1000000000 / pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
/* Program HDMI encoder */
ret = diu_set_dvi_encoder(temp);
if (ret) {
puts("Failed to set DVI encoder\n");
return;
}
/* Program pixel clock */
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
((pixval << PXCK_BITS_START) & PXCK_MASK));
/* enable clock*/
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
((pixval << PXCK_BITS_START) & PXCK_MASK));
}
static ulong ns2clks(ulong ns)
{
ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
}
/*
* Autodetect onboard SDRAM on 405 platforms
*/
phys_size_t initdram(int board_type)
{
ulong speed;
ulong sdtr1;
int i;
/*
* Determine SDRAM speed
*/
speed = get_bus_freq(0); /* parameter not used on ppc4xx */
/*
* sdtr1 (register SDRAM0_TR) must take into account timings listed
* in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
* account actual SDRAM size. So we can set up sdtr1 according to what
* is specified in board configuration file while rtr dependds on SDRAM
* size we are assuming before detection.
*/
sdtr1 = compute_sdtr1(speed);
for (i=0; i<N_MB0CF; i++) {
/*
* Disable memory controller.
*/
mtsdram(SDRAM0_CFG, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
mtsdram(SDRAM0_TR, sdtr1);
mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200);
/*
* Set memory controller options reg, MCOPT1.
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
mtsdram(SDRAM0_CFG, 0x80800000);
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
phys_size_t size = mb0cf[i].size;
/*
* OK, size detected. Enable second bank if
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
mtsdram(SDRAM0_CFG, 0x00000000);
mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
mtsdram(SDRAM0_CFG, 0x80800000);
udelay(10000);
/*
* Check if 2nd bank is really available.
* If the size not equal to the size of the first
* bank, then disable the 2nd bank completely.
*/
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
mb0cf[i].size) {
mtsdram(SDRAM0_B1CR, 0);
mtsdram(SDRAM0_CFG, 0);
} else {
/*
* We have two identical banks, so the size
* is twice the bank size
*/
size = 2 * size;
}
#endif
/*
* OK, size detected -> all done
*/
return size;
}
}
return 0;
}
static int __devinit fs_enet_mdio_probe(struct of_device *ofdev,
const struct of_device_id *match)
{
struct resource res;
struct mii_bus *new_bus;
struct fec_info *fec;
int (*get_bus_freq)(struct device_node *) = match->data;
int ret = -ENOMEM, clock, speed;
new_bus = mdiobus_alloc();
if (!new_bus)
goto out;
fec = kzalloc(sizeof(struct fec_info), GFP_KERNEL);
if (!fec)
goto out_mii;
new_bus->priv = fec;
new_bus->name = "FEC MII Bus";
new_bus->read = &fs_enet_fec_mii_read;
new_bus->write = &fs_enet_fec_mii_write;
new_bus->reset = &fs_enet_fec_mii_reset;
ret = of_address_to_resource(ofdev->node, 0, &res);
if (ret)
goto out_res;
snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", res.start);
fec->fecp = ioremap(res.start, res.end - res.start + 1);
if (!fec->fecp)
goto out_fec;
if (get_bus_freq) {
clock = get_bus_freq(ofdev->node);
if (!clock) {
dev_warn(&ofdev->dev, "could not determine IPS clock\n");
clock = 0x3F * 5000000;
}
} else
clock = ppc_proc_freq;
speed = (clock + 4999999) / 5000000;
if (speed > 0x3F) {
speed = 0x3F;
dev_err(&ofdev->dev,
"MII clock (%d Hz) exceeds max (2.5 MHz)\n",
clock / speed);
}
fec->mii_speed = speed << 1;
setbits32(&fec->fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
setbits32(&fec->fecp->fec_ecntrl, FEC_ECNTRL_PINMUX |
FEC_ECNTRL_ETHER_EN);
out_be32(&fec->fecp->fec_ievent, FEC_ENET_MII);
clrsetbits_be32(&fec->fecp->fec_mii_speed, 0x7E, fec->mii_speed);
new_bus->phy_mask = ~0;
new_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
if (!new_bus->irq)
goto out_unmap_regs;
new_bus->parent = &ofdev->dev;
dev_set_drvdata(&ofdev->dev, new_bus);
ret = of_mdiobus_register(new_bus, ofdev->node);
if (ret)
goto out_free_irqs;
return 0;
out_free_irqs:
dev_set_drvdata(&ofdev->dev, NULL);
kfree(new_bus->irq);
out_unmap_regs:
iounmap(fec->fecp);
out_res:
out_fec:
kfree(fec);
out_mii:
mdiobus_free(new_bus);
out:
return ret;
}
/*-----------------------------------------------------------------------------
* Function: initdram
* Description: Configures SDRAM memory banks for DDR operation.
* Auto Memory Configuration option reads the DDR SDRAM EEPROMs
* via the IIC bus and then configures the DDR SDRAM memory
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
phys_size_t initdram(int board_type)
{
unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_ranks[MAXDIMMS];
unsigned long ranks;
unsigned long rows;
unsigned long banks;
unsigned long cols;
unsigned long width;
unsigned long const sdram_freq = get_bus_freq(0);
unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */
unsigned long cas_latency = 0; /* to quiet initialization warning */
unsigned long dram_size;
debug("\nEntering initdram()\n");
/*------------------------------------------------------------------
* Stop the DDR-SDRAM controller.
*-----------------------------------------------------------------*/
mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));
/*
* Make sure I2C controller is initialized
* before continuing.
*/
/* switch to correct I2C bus */
I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/*------------------------------------------------------------------
* Clear out the serial presence detect buffers.
* Perform IIC reads from the dimm. Fill in the spds.
* Check to see if the dimm slots are populated
*-----------------------------------------------------------------*/
get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);
/*------------------------------------------------------------------
* Check the frequency supported for the dimms plugged.
*-----------------------------------------------------------------*/
check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
/*------------------------------------------------------------------
* Check and get size information.
*-----------------------------------------------------------------*/
get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
&cols, &width);
/*------------------------------------------------------------------
* Check the voltage type for the dimms plugged.
*-----------------------------------------------------------------*/
check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);
/*------------------------------------------------------------------
* Program registers for SDRAM controller.
*-----------------------------------------------------------------*/
mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
DDR0_00_DLL_START_POINT_DECODE(0x0A));
mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
DDR0_01_INT_MASK_ENCODE(0xFF));
program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
rows, &cas_latency);
program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
/*
* TODO: tFAW not found in SPD. Value of 13 taken from Sequoia
* board SDRAM, but may be overly conservative.
*/
mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
DDR0_07_TFAW_ENCODE(13) |
DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
DDR0_07_AREFRESH_ENCODE(0));
mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
DDR0_08_DDRII_ENCODE(1));
mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
DDR0_09_RTT_0_ENCODE(0x1) |
DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));
program_ddr0_10(dimm_ranks, ranks);
program_ddr0_11(sdram_freq);
mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));
mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
DDR0_14_REG_DIMM_ENABLE_ENCODE(0));
mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));
mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));
mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));
mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));
mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));
program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);
mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
DDR0_23_FWC_ENCODE(0));
program_ddr0_24(ranks);
program_ddr0_26(sdram_freq);
program_ddr0_27(sdram_freq);
mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
DDR0_28_EMRS2_DATA_ENCODE(0x0000));
mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) |
DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
cols, banks);
program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
denali_sdram_register_dump();
dram_size = (width >= 64) ? 8 : 4;
dram_size *= 1 << cols;
dram_size *= banks;
dram_size *= 1 << rows;
dram_size *= ranks;
debug("dram_size = %lu\n", dram_size);
/* Start the SDRAM controler */
mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
denali_wait_for_dlllock();
#if defined(CONFIG_DDR_DATA_EYE)
/*
* Map the first 1 MiB of memory in the TLB, and perform the data eye
* search.
*/
program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
denali_core_search_data_eye();
denali_sdram_register_dump();
remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
#endif
#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
sync();
/* Zero the memory */
debug("Zeroing SDRAM...");
#if defined(CONFIG_SYS_MEM_TOP_HIDE)
dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
#else
#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
#endif
/* Write modified dcache lines back to memory */
clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
debug("Completed\n");
sync();
remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
#if defined(CONFIG_DDR_ECC)
/*
* If ECC is enabled, clear and enable interrupts
*/
if (is_ecc_enabled()) {
u32 val;
sync();
/* Clear error status */
mfsdram(DDR0_00, val);
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
/* Set 'int_mask' parameter to functionnal value */
mfsdram(DDR0_01, val);
mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
DDR0_01_INT_MASK_ALL_OFF);
#if defined(CONFIG_DDR_DATA_EYE)
/*
* Running denali_core_search_data_eye() when ECC is enabled
* causes non-ECC machine checks. This clears them.
*/
print_mcsr();
mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
print_mcsr();
#endif
sync();
}
#endif /* defined(CONFIG_DDR_ECC) */
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
return dram_size;
}
void serial_setbrg (void)
{
int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate;
NS16550_reinit (console, clock_divisor);
}
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
phys_size_t initdram (int board_type)
{
unsigned char data[2];
unsigned int chip, v, t, i, x, sz, ms, rr, rf, st;
unsigned long speed;
unsigned char mt, bl, cl, rk, tmp; /* memory type, burst length, cas latency, ranks */
unsigned char map[3] = { SPD_TAC0, SPD_TAC1, SPD_TAC2 };
#ifdef DEBUG
unsigned int j;
#endif
chip = SPD_EEPROM_ADDRESS;
debug("dram: about to probe chip 0x%x\n", chip);
if(check_sane_spd(chip)){
printf("dram: nonexistent or unusable spd eeprom\n");
hang();
}
#ifdef DEBUG
debug("dram: raw");
for(j = 0; j < 64; j++){
if(i2c_read(chip, j, 1, data, 1) == 0){
debug("%c%02x", (j % 16) ? ' ' : '\n', data[0]);
}
}
debug("\n");
#endif
/* rushed dump from spd to ddr controller, calculations hardwired from sequoia and generally iffy */
if(i2c_read(chip, SPD_MEMORY_TYPE, 1, data, 1) != 0){
return 0;
}
mt = data[0];
switch(mt){
case SPD_MEMORY_TYPE_DDR2_SDRAM :
debug("dram: ddr2 memory\n");
break;
/* case SPD_MEMORY_TYPE_DDR_SDRAM : */
default :
printf("dram: unsupported memory type 0x%x\n", mt);
return 0;
}
speed = get_bus_freq(0);
debug("dram: bus speed %luHz\n", speed);
if(i2c_read(chip, SPD_REFRESH_RATE, 1, data, 1) != 0){
return 0;
}
rr = decode_refresh(data[0]);
debug("dram: refresh rate %ups\n", rr);
xmtsdram(DDR0_02, DDR0_02_START_OFF);
mfsdram(DDR0_02, ms);
/* gives us the maximum dimensions the controller can do, used later */
debug("dram: controller caps 0x%08x\n", ms);
/* calibration values as recommended */
xmtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) | DDR0_00_DLL_START_POINT_ENCODE(0xa));
/* set as required, possibly could set up interrupt masks */
xmtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x1) | DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0));
v = 0;
v |= DDR0_03_INITAREF_ENCODE(0x2); /* WARNING: no idea how many autorefresh commands needed during initialisation */
if(i2c_read(chip, SPD_BURST_LENGTHS, 1, data, 1) != 0){
return 0;
}
bl = ((mt != SPD_MEMORY_TYPE_DDR2_SDRAM) && (data[0] & SPD_BURST_LENGTH_8)) ? 8 : 4;
debug("dram: burst length caps=0x%x, chosen=%d\n", data[0], bl);
v |= DDR0_03_BSTLEN_ENCODE((bl == 8) ? 0x3 : 0x2);
if(i2c_read(chip, SPD_CAS_LATENCIES, 1, data, 1) != 0){
return 0;
}
cl = 0;
tmp = data[0];
debug("dram: latency choices 0x%x\n", tmp);
/* could use a less agressive mode by quitting for a lower x */
for(i = 7, x = 0; (i >= 2) && (x < 3); i--){
if(tmp & (0x1 << i)){
debug("dram: can do cl=%d\n", i);
if(i2c_read(chip, map[x] + 1, 1, data, 1) != 0){
return 0;
}
t = ps2cycles(speed, (((data[0] >> 4) & 0xf) * 100) + ((data[0] & 0xf) * 10), "minclock");
if(t > 0){
debug("dram: clock too fast for cl-%d\n", x);
break;
}
cl = i;
x++;
}
}
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_bus_freq(0);
}
void ft_cpu_setup(void *blob, bd_t *bd)
{
int off;
int val;
const char *sysclk_path;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
unsigned int svr;
svr = in_be32(&gur->svr);
unsigned long busclk = get_bus_freq(0);
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(svr))
fdt_fixup_crypto_node(blob, 0);
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
else {
ccsr_sec_t __iomem *sec;
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
val = gd->cpu_clk;
fdt_setprop(blob, off, "clock-frequency", &val, 4);
off = fdt_node_offset_by_prop_value(blob, off,
"device_type", "cpu", 4);
}
do_fixup_by_prop_u32(blob, "device_type", "soc",
4, "bus-frequency", busclk, 1);
ft_fixup_enet_phy_connect_type(blob);
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif
sysclk_path = fdt_get_alias(blob, "sysclk");
if (sysclk_path)
do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
CONFIG_SYS_CLK_FREQ, 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
#define UBOOT_HEAD_LEN 0x1000
/*
* Reserved memory in SD boot deep sleep case.
* Second stage uboot binary and malloc space should be reserved.
* If the memory they occupied has not been reserved, then this
* space would be used by kernel and overwritten in uboot when
* deep sleep resume, which cause deep sleep failed.
* Since second uboot binary has a head, that space need to be
* reserved either(assuming its size is less than 0x1000).
*/
off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
UBOOT_HEAD_LEN);
if (off < 0)
printf("Failed to reserve memory for SD boot deep sleep: %s\n",
fdt_strerror(off));
#endif
#if defined(CONFIG_FSL_ESDHC)
fdt_fixup_esdhc(blob, bd);
#endif
/*
* platform bus clock = system bus clock/2
* Here busclk = system bus clock
* We are using the platform bus clock as 1588 Timer reference
* clock source select
*/
do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
"timer-frequency", busclk / 2, 1);
/*
* clock-freq should change to clock-frequency and
* flexcan-v1.0 should change to p1010-flexcan respectively
* in the future.
*/
do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
"clock_freq", busclk / 2, 1);
do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
"clock-frequency", busclk / 2, 1);
do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
"clock-frequency", busclk / 2, 1);
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
CONFIG_SYS_IFC_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
#else
off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
QSPI0_BASE_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
DSPI1_BASE_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
#endif
}
static int fs_enet_mdio_probe(struct platform_device *ofdev)
{
const struct of_device_id *match;
struct resource res;
struct mii_bus *new_bus;
struct fec_info *fec;
int (*get_bus_freq)(struct device_node *);
int ret = -ENOMEM, clock, speed;
match = of_match_device(fs_enet_mdio_fec_match, &ofdev->dev);
if (!match)
return -EINVAL;
get_bus_freq = match->data;
new_bus = mdiobus_alloc();
if (!new_bus)
goto out;
fec = kzalloc(sizeof(struct fec_info), GFP_KERNEL);
if (!fec)
goto out_mii;
new_bus->priv = fec;
new_bus->name = "FEC MII Bus";
new_bus->read = &fs_enet_fec_mii_read;
new_bus->write = &fs_enet_fec_mii_write;
ret = of_address_to_resource(ofdev->dev.of_node, 0, &res);
if (ret)
goto out_res;
snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", res.start);
fec->fecp = ioremap(res.start, resource_size(&res));
if (!fec->fecp) {
ret = -ENOMEM;
goto out_fec;
}
if (get_bus_freq) {
clock = get_bus_freq(ofdev->dev.of_node);
if (!clock) {
/* Use maximum divider if clock is unknown */
dev_warn(&ofdev->dev, "could not determine IPS clock\n");
clock = 0x3F * 5000000;
}
} else
clock = ppc_proc_freq;
/*
* Scale for a MII clock <= 2.5 MHz
* Note that only 6 bits (25:30) are available for MII speed.
*/
speed = (clock + 4999999) / 5000000;
if (speed > 0x3F) {
speed = 0x3F;
dev_err(&ofdev->dev,
"MII clock (%d Hz) exceeds max (2.5 MHz)\n",
clock / speed);
}
fec->mii_speed = speed << 1;
setbits32(&fec->fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
setbits32(&fec->fecp->fec_ecntrl, FEC_ECNTRL_PINMUX |
FEC_ECNTRL_ETHER_EN);
out_be32(&fec->fecp->fec_ievent, FEC_ENET_MII);
clrsetbits_be32(&fec->fecp->fec_mii_speed, 0x7E, fec->mii_speed);
new_bus->phy_mask = ~0;
new_bus->parent = &ofdev->dev;
platform_set_drvdata(ofdev, new_bus);
ret = of_mdiobus_register(new_bus, ofdev->dev.of_node);
if (ret)
goto out_unmap_regs;
return 0;
out_unmap_regs:
iounmap(fec->fecp);
out_res:
out_fec:
kfree(fec);
out_mii:
mdiobus_free(new_bus);
out:
return ret;
}
static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
struct device_node *np;
int i, count;
u32 freq;
struct clk *clk;
const struct clk_hw *hwclk;
struct cpufreq_frequency_table *table;
struct cpu_data *data;
unsigned int cpu = policy->cpu;
u64 u64temp;
np = of_get_cpu_node(cpu, NULL);
if (!np)
return -ENODEV;
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
goto err_np;
policy->clk = of_clk_get(np, 0);
if (IS_ERR(policy->clk)) {
pr_err("%s: no clock information\n", __func__);
goto err_nomem2;
}
hwclk = __clk_get_hw(policy->clk);
count = clk_hw_get_num_parents(hwclk);
data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
if (!data->pclk)
goto err_nomem2;
table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
if (!table)
goto err_pclk;
for (i = 0; i < count; i++) {
clk = clk_hw_get_parent_by_index(hwclk, i)->clk;
data->pclk[i] = clk;
freq = clk_get_rate(clk);
table[i].frequency = freq / 1000;
table[i].driver_data = i;
}
freq_table_redup(table, count);
freq_table_sort(table, count);
table[i].frequency = CPUFREQ_TABLE_END;
policy->freq_table = table;
data->table = table;
/* update ->cpus if we have cluster, no harm if not */
set_affected_cpus(policy);
policy->driver_data = data;
/* Minimum transition latency is 12 platform clocks */
u64temp = 12ULL * NSEC_PER_SEC;
do_div(u64temp, get_bus_freq());
policy->cpuinfo.transition_latency = u64temp + 1;
of_node_put(np);
return 0;
err_pclk:
kfree(data->pclk);
err_nomem2:
kfree(data);
err_np:
of_node_put(np);
return -ENODEV;
}
/*
* initdram -- 440EPx's DDR controller is a DENALI Core
*/
int initdram_by_rb(int rows, int banks)
{
ulong speed = get_bus_freq(0);
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
mtsdram(DDR0_01, 0x01000000);
mtsdram(DDR0_03, 0x02030602);
mtsdram(DDR0_04, 0x0A020200);
mtsdram(DDR0_05, 0x02020308);
mtsdram(DDR0_06, 0x0102C812);
mtsdram(DDR0_07, 0x000D0100);
mtsdram(DDR0_08, 0x02430001);
mtsdram(DDR0_09, 0x00011D5F);
mtsdram(DDR0_10, 0x00000100);
mtsdram(DDR0_11, 0x0027C800);
mtsdram(DDR0_12, 0x00000003);
mtsdram(DDR0_14, 0x00000000);
mtsdram(DDR0_17, 0x19000000);
mtsdram(DDR0_18, 0x19191919);
mtsdram(DDR0_19, 0x19191919);
mtsdram(DDR0_20, 0x0B0B0B0B);
mtsdram(DDR0_21, 0x0B0B0B0B);
mtsdram(DDR0_22, 0x00267F0B);
mtsdram(DDR0_23, 0x00000000);
mtsdram(DDR0_24, 0x01010002);
if (speed > 133333334)
mtsdram(DDR0_26, 0x5B26050C);
else
mtsdram(DDR0_26, 0x5B260408);
mtsdram(DDR0_27, 0x0000682B);
mtsdram(DDR0_28, 0x00000000);
mtsdram(DDR0_31, 0x00000000);
mtsdram(DDR0_42,
DDR0_42_ADDR_PINS_DECODE(14 - rows) |
0x00000006);
mtsdram(DDR0_43,
DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
0x030A0200);
mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001);
denali_wait_for_dlllock();
#ifdef CONFIG_DDR_DATA_EYE
/*
* Perform data eye search if requested.
*/
denali_core_search_data_eye();
#endif
/*
* Clear possible errors resulting from data-eye-search.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
set_mcsr(get_mcsr());
return 0;
}
