static int gator_events_clock_read(int **buffer, bool sched_switch)
{
int i;
int len = 0;
/* System wide counters - read from one core only */
if (!on_primary_core() || !clock_global_enabled)
return 0;
for (i = 0; i < CLOCK_COUNTERS_NUM; i++) {
if (clock_counters[i].enabled) {
clock_buffer[len++] = clock_counters[i].key;
clock_buffer[len++] =
get_clock_value(i);
}
}
if (buffer)
*buffer = clock_buffer;
return len;
}
uint32_t
zynq_get_clock(enum zynq_clocks name)
{
struct zynqslcr_softc *sc = slcr_softc;
struct zynq7000_clock_info *clk = sc->sc_clk_info;
uint32_t reg;
if (slcr_softc == NULL)
return -1;
switch (name) {
case CLK_PS:
return clk->clk_ps;
case CLK_ARM_PLL:
if (clk->clk_arm_base == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_ARM_PLL_CTRL);
clk->clk_arm_base = __SHIFTOUT(reg, PLL_FDIV) * clk->clk_ps;
}
return clk->clk_arm_base;
case CLK_DDR_PLL:
if (clk->clk_ddr_base == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_DDR_PLL_CTRL);
clk->clk_ddr_base = __SHIFTOUT(reg, PLL_FDIV) * clk->clk_ps;
}
return clk->clk_ddr_base;
case CLK_IO_PLL:
if (clk->clk_io_base == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_IO_PLL_CTRL);
clk->clk_io_base = __SHIFTOUT(reg, PLL_FDIV) * clk->clk_ps;
}
return clk->clk_io_base;
case CLK_CPU_6X4X:
if (clk->clk_cpu_6x4x == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_ARM_CLK_CTRL);
clk->clk_cpu_6x4x = zynq_get_clock(CLK_ARM_PLL) / __SHIFTOUT(reg, CLK_DIVISOR0);
}
return clk->clk_cpu_6x4x;
case CLK_CPU_3X2X:
if (clk->clk_cpu_3x2x == 0)
clk->clk_cpu_3x2x = zynq_get_clock(CLK_CPU_6X4X) / 2;
return clk->clk_cpu_3x2x;
case CLK_CPU_2X:
if (clk->clk_cpu_2x == 0)
clk->clk_cpu_2x = zynq_get_clock(CLK_CPU_6X4X) / 3;
return clk->clk_cpu_2x;
case CLK_CPU_1X:
if (clk->clk_cpu_1x == 0)
clk->clk_cpu_1x = zynq_get_clock(CLK_CPU_6X4X) / 6;
return clk->clk_cpu_1x;
case CLK_DDR_3X:
if (clk->clk_ddr_3x == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_DDR_CLK_CTRL);
clk->clk_ddr_3x = zynq_get_clock(CLK_DDR_PLL) / __SHIFTOUT(reg, CLK_DDR_3XCLK_DIVISO);
}
return clk->clk_ddr_3x;
case CLK_DDR_2X:
if (clk->clk_ddr_2x == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_DDR_CLK_CTRL);
clk->clk_ddr_2x = zynq_get_clock(CLK_DDR_PLL) / __SHIFTOUT(reg, CLK_DDR_2XCLK_DIVISO);
}
return clk->clk_ddr_2x;
case CLK_DDR_DCI:
if (clk->clk_ddr_dci == 0)
clk->clk_ddr_dci = get_clock_value(sc, CLK_DDR_PLL, SLCR_DCI_CLK_CTRL);
return clk->clk_ddr_dci;
case CLK_SMC:
if (clk->clk_smc == 0)
clk->clk_smc = get_clock_value(sc, CLK_IO_PLL, SLCR_SMC_CLK_CTRL);
return clk->clk_smc;
case CLK_QSPI:
if (clk->clk_qspi == 0)
clk->clk_qspi = get_clock_value(sc, CLK_IO_PLL, SLCR_LQSPI_CLK_CTRL);
return clk->clk_qspi;
case CLK_GIGE0:
if (clk->clk_gige0 == 0)
clk->clk_gige0 = get_clock_value(sc, CLK_IO_PLL, SLCR_GEM0_CLK_CTRL);
return clk->clk_gige0;
case CLK_GIGE1:
if (clk->clk_gige1 == 0)
clk->clk_gige1 = get_clock_value(sc, CLK_IO_PLL, SLCR_GEM1_CLK_CTRL);
return clk->clk_gige1;
case CLK_SDIO:
if (clk->clk_sdio == 0)
clk->clk_sdio = get_clock_value(sc, CLK_IO_PLL, SLCR_SDIO_CLK_CTRL);
return clk->clk_sdio;
case CLK_UART:
if (clk->clk_uart == 0)
clk->clk_uart = get_clock_value(sc, CLK_IO_PLL, SLCR_UART_CLK_CTRL);
return clk->clk_uart;
case CLK_SPI:
if (clk->clk_spi == 0)
clk->clk_spi = get_clock_value(sc, CLK_IO_PLL, SLCR_SPI_CLK_CTRL);
return clk->clk_spi;
case CLK_CAN:
if (clk->clk_can == 0)
clk->clk_can = get_clock_value(sc, CLK_IO_PLL, SLCR_CAN_CLK_CTRL);
return clk->clk_can;
case CLK_PCAP:
if (clk->clk_pcap == 0)
clk->clk_pcap = get_clock_value(sc, CLK_IO_PLL, SLCR_PCAP_CLK_CTRL);
return clk->clk_pcap;
case CLK_DBG:
if (clk->clk_dbg == 0)
clk->clk_dbg = get_clock_value(sc, CLK_IO_PLL, SLCR_DBG_CLK_CTRL);
return clk->clk_dbg;
case CLK_FCLK0:
if (clk->clk_fclk0 == 0)
clk->clk_fclk0 = get_clock_value(sc, CLK_IO_PLL, SLCR_FPGA0_CLK_CTRL);
return clk->clk_fclk0;
case CLK_FCLK1:
if (clk->clk_fclk1 == 0)
clk->clk_fclk1 = get_clock_value(sc, CLK_IO_PLL, SLCR_FPGA1_CLK_CTRL);
return clk->clk_fclk1;
case CLK_FCLK2:
if (clk->clk_fclk2 == 0)
clk->clk_fclk2 = get_clock_value(sc, CLK_IO_PLL, SLCR_FPGA2_CLK_CTRL);
return clk->clk_fclk2;
case CLK_FCLK3:
if (clk->clk_fclk3 == 0)
clk->clk_fclk3 = get_clock_value(sc, CLK_IO_PLL, SLCR_FPGA3_CLK_CTRL);
return clk->clk_fclk3;
default:
return -1;
}
}
