void NAND_WAIT_READY()
{
if (get_cm_rev() == 'A')
while (!(*(volatile unsigned int *)AT91C_PIOD_PDSR & AT91C_PIO_PD6))
;
else
while (!(*(volatile unsigned int *)AT91C_PIOD_PDSR & AT91C_PIO_PD5))
;
}
void NAND_WAIT_READY()
{
if ((get_cm_rev() == 'A') && (get_cm_vendor() == VENDOR_EMBEST))
while (!(*(volatile unsigned int *)AT91C_PIOD_PDSR & AT91C_PIO_PD6))
;
else
while (!(*(volatile unsigned int *)AT91C_PIOD_PDSR & AT91C_PIO_PD5))
;
}
void nandflash_hw_init(void)
{
unsigned int reg;
/* Configure Nand PINs */
const struct pio_desc nand_pins_hi[] = {
{"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{"D0", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D1", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D2", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D3", AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D4", AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D5", AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D6", AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D7", AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
const struct pio_desc nand_pins_lo[] = {
{"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
if (get_cm_rev() == 'A')
reg &= ~AT91C_EBI_NFD0_ON_D16;
else
reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
reg &= ~AT91C_EBI_DRV;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(1)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(2)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(3)
| AT91C_SMC_NCS_WRPULSE_(5)
| AT91C_SMC_NRDPULSE_(4)
| AT91C_SMC_NCS_RDPULSE_(6)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(7)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| AT91C_SMC_DBW_WIDTH_BITS_8
| AT91_SMC_TDF_(1)),
AT91C_BASE_SMC + SMC_CTRL3);
/* Configure the PIO controller */
if (get_cm_rev() == 'A')
pio_configure(nand_pins_lo);
else
pio_configure(nand_pins_hi);
pmc_enable_periph_clock(AT91C_ID_PIOC_D);
}
/*------------------------------------------------------------------------------*/
void nandflash_hw_init(void)
{
unsigned int reg;
/*
* Configure PIOs
*/
const struct pio_desc nand_pio_hi[] = {
{"NANDOE", AT91C_PIN_PD(0), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", AT91C_PIN_PD(1), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", AT91C_PIN_PD(2), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PD(3), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", AT91C_PIN_PD(4), 0, PIO_PULLUP, PIO_OUTPUT},
{"RDY_BSY", AT91C_PIN_PD(5), 0, PIO_PULLUP, PIO_INPUT},
{"D0", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D1", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D2", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D3", AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D4", AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D5", AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D6", AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D7", AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
const struct pio_desc nand_pio_lo[] = {
{"NANDOE", AT91C_PIN_PD(0), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", AT91C_PIN_PD(1), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", AT91C_PIN_PD(2), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PD(3), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", AT91C_PIN_PD(4), 0, PIO_PULLUP, PIO_OUTPUT},
{"RDY_BSY", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_INPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
if (get_cm_rev() == 'A') {
reg &= ~AT91C_EBI_NFD0_ON_D16;
} else {
reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
}
reg &= ~AT91C_EBI_DRV;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/*
* Configure SMC CS3
*/
writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP |
AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE |
AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE |
AT91C_SMC_NWAITM_NWAIT_DISABLE | AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
AT91C_SM_TDF), AT91C_BASE_SMC + SMC_CTRL3);
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
if (get_cm_rev() == 'A')
pio_setup(nand_pio_lo);
else
pio_setup(nand_pio_hi);
nand_recovery();
}
