/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_PANDORA();
if (get_cpu_family() == CPU_OMAP36XX) {
MUX_PANDORA_3730();
}
}
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
t2_t *t2_base = (t2_t *)T2_BASE;
u32 pbias_lite;
twl4030_power_init();
/* set VSIM to 1.8V */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
TWL4030_PM_RECEIVER_VSIM_VSEL_18,
TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
/* set up dual-voltage GPIOs to 1.8V */
pbias_lite = readl(&t2_base->pbias_lite);
pbias_lite &= ~PBIASLITEVMODE1;
pbias_lite |= PBIASLITEPWRDNZ1;
writel(pbias_lite, &t2_base->pbias_lite);
if (get_cpu_family() == CPU_OMAP36XX)
writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
OMAP34XX_CTRL_WKUP_CTRL);
setup_net_chip();
omap_die_id_display();
set_led();
set_boardname();
return 0;
}
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
int mfr, id, err = identify_nand_chip(&mfr, &id);
timings->mr = MICRON_V_MR_165;
if (!err && mfr == NAND_MFR_MICRON) {
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
} else {
if (get_cpu_family() == CPU_OMAP34XX) {
timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_165;
timings->ctrlb = NUMONYX_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else {
timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_200;
timings->ctrlb = NUMONYX_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}
gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
}
}
void set_muxconf_regs(void)
{
cm_t3x_set_common_muxconf();
if (get_cpu_family() == CPU_OMAP34XX)
cm_t35_set_muxconf();
else
cm_t3730_set_muxconf();
}
int omap_mmc_init(int dev_index)
{
struct mmc *mmc;
mmc = &hsmmc_dev[dev_index];
sprintf(mmc->name, "OMAP SD/MMC");
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_init_setup;
switch (dev_index) {
case 0:
mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
break;
case 1:
mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE;
break;
case 2:
mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE;
break;
default:
mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
return 1;
}
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
mmc->f_max = 52000000;
mmc->b_max = 0;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
mmc->b_max = 1;
#endif
mmc_register(mmc);
return 0;
}
/*
* Routine: board_init
* Description: hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
if (get_cpu_family() == CPU_OMAP34XX)
gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
else
gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
#endif
return 0;
}
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
t2_t *t2_base = (t2_t *)T2_BASE;
u32 pbias_lite;
twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
/* set up dual-voltage GPIOs to 1.8V */
pbias_lite = readl(&t2_base->pbias_lite);
pbias_lite &= ~PBIASLITEVMODE1;
pbias_lite |= PBIASLITEPWRDNZ1;
writel(pbias_lite, &t2_base->pbias_lite);
if (get_cpu_family() == CPU_OMAP36XX)
writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
CONTROL_WKUP_CTRL);
/* make sure audio and BT chips are in powerdown state */
set_output_gpio(14, 0);
set_output_gpio(15, 0);
set_output_gpio(118, 0);
/* enable USB supply */
set_output_gpio(164, 1);
/* wifi needs a short pulse to enter powersave state */
set_output_gpio(23, 1);
udelay(5000);
gpio_direction_output(23, 0);
/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
TWL4030_PM_RECEIVER_BB_CFG,
TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
TWL4030_BB_CFG_BBISEL_500UA);
omap_die_id_display();
return 0;
}
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
printf("mvBlueLYNX-X\n");
if (get_cpu_family() == CPU_OMAP36XX)
setenv("mpurate", "1000");
else
setenv("mpurate", "600");
twl4030_power_init();
#if defined(CONFIG_CMD_NET)
setup_net_chip();
#endif /* CONFIG_CMD_NET */
mvblx_init_fpga();
mac_read_from_eeprom();
dieid_num_r();
return 0;
}
/*
* Routine: board_init
* Description: hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
/* board id for Linux */
if (get_cpu_family() == CPU_OMAP34XX)
gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
else
gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
#endif
return 0;
}
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
int mfr, id, err = identify_nand_chip(&mfr, &id);
timings->mr = MICRON_V_MR_165;
if (!err) {
switch (mfr) {
case NAND_MFR_HYNIX:
timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
timings->ctrla = HYNIX_V_ACTIMA_200;
timings->ctrlb = HYNIX_V_ACTIMB_200;
break;
case NAND_MFR_MICRON:
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
break;
default:
/* Should not happen... */
break;
}
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
} else {
if (get_cpu_family() == CPU_OMAP34XX) {
timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_165;
timings->ctrlb = NUMONYX_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else {
timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_200;
timings->ctrlb = NUMONYX_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}
gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
}
}
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
timings->mr = MICRON_V_MR_165;
#ifdef CONFIG_BOOT_NAND
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else
if (get_cpu_family() == CPU_OMAP34XX) {
timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_165;
timings->ctrlb = NUMONYX_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else {
timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_200;
timings->ctrlb = NUMONYX_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}
#endif
}
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)
{
*mr = MICRON_V_MR_165;
#ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_200(256 << 20);
*ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else
if (get_cpu_family() == CPU_OMAP34XX) {
*mcfg = NUMONYX_V_MCFG_165(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_165;
*ctrlb = NUMONYX_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else {
*mcfg = NUMONYX_V_MCFG_200(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_200;
*ctrlb = NUMONYX_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}
#endif
}
static int omap_hsmmc_set_ios(struct mmc *mmc)
{
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
#else
static int omap_hsmmc_set_ios(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = upriv->mmc;
#endif
struct hsmmc *mmc_base;
unsigned int dsor = 0;
ulong start;
mmc_base = priv->base_addr;
/* configue bus width */
switch (mmc->bus_width) {
case 8:
writel(readl(&mmc_base->con) | DTW_8_BITMODE,
&mmc_base->con);
break;
case 4:
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
&mmc_base->con);
writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
&mmc_base->hctl);
break;
case 1:
default:
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
&mmc_base->con);
writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
&mmc_base->hctl);
break;
}
/* configure clock with 96Mhz system clock.
*/
if (mmc->clock != 0) {
dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
dsor++;
}
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for ics!\n", __func__);
return -ETIMEDOUT;
}
}
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
return 0;
}
#ifdef OMAP_HSMMC_USE_GPIO
#if CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_getcd(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
int value;
value = dm_gpio_get_value(&priv->cd_gpio);
/* if no CD return as 1 */
if (value < 0)
return 1;
if (priv->cd_inverted)
return !value;
return value;
}
static int omap_hsmmc_getwp(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
int value;
value = dm_gpio_get_value(&priv->wp_gpio);
/* if no WP return as 0 */
if (value < 0)
return 0;
return value;
}
#else
static int omap_hsmmc_getcd(struct mmc *mmc)
{
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
int cd_gpio;
/* if no CD return as 1 */
cd_gpio = priv->cd_gpio;
if (cd_gpio < 0)
return 1;
/* NOTE: assumes card detect signal is active-low */
return !gpio_get_value(cd_gpio);
}
static int omap_hsmmc_getwp(struct mmc *mmc)
{
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
int wp_gpio;
/* if no WP return as 0 */
wp_gpio = priv->wp_gpio;
if (wp_gpio < 0)
return 0;
/* NOTE: assumes write protect signal is active-high */
return gpio_get_value(wp_gpio);
}
#endif
#endif
#if CONFIG_IS_ENABLED(DM_MMC)
static const struct dm_mmc_ops omap_hsmmc_ops = {
.send_cmd = omap_hsmmc_send_cmd,
.set_ios = omap_hsmmc_set_ios,
#ifdef OMAP_HSMMC_USE_GPIO
.get_cd = omap_hsmmc_getcd,
.get_wp = omap_hsmmc_getwp,
#endif
};
#else
static const struct mmc_ops omap_hsmmc_ops = {
.send_cmd = omap_hsmmc_send_cmd,
.set_ios = omap_hsmmc_set_ios,
.init = omap_hsmmc_init_setup,
#ifdef OMAP_HSMMC_USE_GPIO
.getcd = omap_hsmmc_getcd,
.getwp = omap_hsmmc_getwp,
#endif
};
#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio)
{
struct mmc *mmc;
struct omap_hsmmc_data *priv;
struct mmc_config *cfg;
uint host_caps_val;
priv = malloc(sizeof(*priv));
if (priv == NULL)
return -1;
host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
switch (dev_index) {
case 0:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
break;
#ifdef OMAP_HSMMC2_BASE
case 1:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
default:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
#ifdef OMAP_HSMMC_USE_GPIO
/* on error gpio values are set to -1, which is what we want */
priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
#endif
cfg = &priv->cfg;
cfg->name = "OMAP SD/MMC";
cfg->ops = &omap_hsmmc_ops;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->host_caps = host_caps_val & ~host_caps_mask;
cfg->f_min = 400000;
if (f_max != 0)
cfg->f_max = f_max;
else {
if (cfg->host_caps & MMC_MODE_HS) {
if (cfg->host_caps & MMC_MODE_HS_52MHz)
cfg->f_max = 52000000;
else
cfg->f_max = 26000000;
} else
cfg->f_max = 20000000;
}
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
cfg->b_max = 1;
#endif
mmc = mmc_create(cfg, priv);
if (mmc == NULL)
return -1;
return 0;
}
#else
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
struct mmc_config *cfg = &plat->cfg;
struct omap2_mmc_platform_config *data =
(struct omap2_mmc_platform_config *)dev_get_driver_data(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int val;
plat->base_addr = map_physmem(devfdt_get_addr(dev),
sizeof(struct hsmmc *),
MAP_NOCACHE) + data->reg_offset;
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
val = fdtdec_get_int(fdt, node, "bus-width", -1);
if (val < 0) {
printf("error: bus-width property missing\n");
return -ENOENT;
}
switch (val) {
case 0x8:
cfg->host_caps |= MMC_MODE_8BIT;
case 0x4:
cfg->host_caps |= MMC_MODE_4BIT;
break;
default:
printf("error: invalid bus-width property\n");
return -ENOENT;
}
cfg->f_min = 400000;
cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
#ifdef OMAP_HSMMC_USE_GPIO
plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
#endif
return 0;
}
#endif
#ifdef CONFIG_BLK
static int omap_hsmmc_bind(struct udevice *dev)
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
#endif
static int omap_hsmmc_probe(struct udevice *dev)
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct omap_hsmmc_data *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
struct mmc *mmc;
cfg->name = "OMAP SD/MMC";
priv->base_addr = plat->base_addr;
#ifdef OMAP_HSMMC_USE_GPIO
priv->cd_inverted = plat->cd_inverted;
#endif
#ifdef CONFIG_BLK
mmc = &plat->mmc;
#else
mmc = mmc_create(cfg, priv);
if (mmc == NULL)
return -1;
#endif
#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif
mmc->dev = dev;
upriv->mmc = mmc;
return omap_hsmmc_init_setup(mmc);
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct omap2_mmc_platform_config omap3_mmc_pdata = {
.reg_offset = 0,
};
static const struct omap2_mmc_platform_config am33xx_mmc_pdata = {
.reg_offset = 0x100,
};
static const struct omap2_mmc_platform_config omap4_mmc_pdata = {
.reg_offset = 0x100,
};
static const struct udevice_id omap_hsmmc_ids[] = {
{
.compatible = "ti,omap3-hsmmc",
.data = (ulong)&omap3_mmc_pdata
},
{
.compatible = "ti,omap4-hsmmc",
.data = (ulong)&omap4_mmc_pdata
},
{
.compatible = "ti,am33xx-hsmmc",
.data = (ulong)&am33xx_mmc_pdata
},
{ }
};
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio)
{
struct mmc *mmc;
struct omap_hsmmc_data *priv_data;
struct mmc_config *cfg;
uint host_caps_val;
priv_data = malloc(sizeof(*priv_data));
if (priv_data == NULL)
return -1;
host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
switch (dev_index) {
case 0:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
break;
#ifdef OMAP_HSMMC2_BASE
case 1:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
default:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
#ifdef OMAP_HSMMC_USE_GPIO
/* on error gpio values are set to -1, which is what we want */
priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
#endif
cfg = &priv_data->cfg;
cfg->name = "OMAP SD/MMC";
cfg->ops = &omap_hsmmc_ops;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->host_caps = host_caps_val & ~host_caps_mask;
cfg->f_min = 400000;
if (f_max != 0)
cfg->f_max = f_max;
else {
if (cfg->host_caps & MMC_MODE_HS) {
if (cfg->host_caps & MMC_MODE_HS_52MHz)
cfg->f_max = 52000000;
else
cfg->f_max = 26000000;
} else
cfg->f_max = 20000000;
}
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
cfg->b_max = 1;
#endif
mmc = mmc_create(cfg, priv_data);
if (mmc == NULL)
return -1;
return 0;
}
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio)
{
struct mmc *mmc = &hsmmc_dev[dev_index];
struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index];
uint host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
MMC_MODE_HC;
sprintf(mmc->name, "OMAP SD/MMC");
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_init_setup;
mmc->priv = priv_data;
switch (dev_index) {
case 0:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
break;
#ifdef OMAP_HSMMC2_BASE
case 1:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
default:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
if (priv_data->cd_gpio != -1)
mmc->getcd = omap_mmc_getcd;
priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
if (priv_data->wp_gpio != -1)
mmc->getwp = omap_mmc_getwp;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = host_caps_val & ~host_caps_mask;
mmc->f_min = 400000;
if (f_max != 0)
mmc->f_max = f_max;
else {
if (mmc->host_caps & MMC_MODE_HS) {
if (mmc->host_caps & MMC_MODE_HS_52MHz)
mmc->f_max = 52000000;
else
mmc->f_max = 26000000;
} else
mmc->f_max = 20000000;
}
mmc->b_max = 0;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
mmc->b_max = 1;
#endif
mmc_register(mmc);
return 0;
}
/******************************************************************************
* peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
*****************************************************************************/
void per_clocks_enable(void)
{
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* Enable GP2 timer. */
sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clocks */
sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
/* UART 3 Clocks */
sr32(&prcm_base->fclken_per, 11, 1, 0x1);
sr32(&prcm_base->iclken_per, 11, 1, 0x1);
#endif
#ifdef CONFIG_OMAP3_GPIO_2
sr32(&prcm_base->fclken_per, 13, 1, 1);
sr32(&prcm_base->iclken_per, 13, 1, 1);
#endif
#ifdef CONFIG_OMAP3_GPIO_3
sr32(&prcm_base->fclken_per, 14, 1, 1);
sr32(&prcm_base->iclken_per, 14, 1, 1);
#endif
#ifdef CONFIG_OMAP3_GPIO_4
sr32(&prcm_base->fclken_per, 15, 1, 1);
sr32(&prcm_base->iclken_per, 15, 1, 1);
#endif
#ifdef CONFIG_OMAP3_GPIO_5
sr32(&prcm_base->fclken_per, 16, 1, 1);
sr32(&prcm_base->iclken_per, 16, 1, 1);
#endif
#ifdef CONFIG_OMAP3_GPIO_6
sr32(&prcm_base->fclken_per, 17, 1, 1);
sr32(&prcm_base->iclken_per, 17, 1, 1);
#endif
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
/* Turn on all 3 I2C clocks */
sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
#endif
/* Enable the ICLK for 32K Sync Timer as its used in udelay */
sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
if (get_cpu_family() != CPU_AM35XX)
sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
if (get_cpu_family() != CPU_AM35XX) {
sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
}
sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
sdelay(1000);
}
static unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_OMAP34XX)
t2_t *t2_base = (t2_t *)T2_BASE;
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
u32 pbias_lite;
#ifdef CONFIG_MMC_OMAP36XX_PINS
u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
#endif
pbias_lite = readl(&t2_base->pbias_lite);
pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
#ifdef CONFIG_TARGET_OMAP3_CAIRO
/* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
pbias_lite &= ~PBIASLITEVMODE0;
#endif
#ifdef CONFIG_MMC_OMAP36XX_PINS
if (get_cpu_family() == CPU_OMAP36XX) {
/* Disable extended drain IO before changing PBIAS */
wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
}
#endif
writel(pbias_lite, &t2_base->pbias_lite);
writel(pbias_lite | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
&t2_base->pbias_lite);
#ifdef CONFIG_MMC_OMAP36XX_PINS
if (get_cpu_family() == CPU_OMAP36XX)
/* Enable extended drain IO after changing PBIAS */
writel(wkup_ctrl |
OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
OMAP34XX_CTRL_WKUP_CTRL);
#endif
writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
&t2_base->devconf0);
writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
&t2_base->devconf1);
/* Change from default of 52MHz to 26MHz if necessary */
if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
&t2_base->ctl_prog_io1);
writel(readl(&prcm_base->fclken1_core) |
EN_MMC1 | EN_MMC2 | EN_MMC3,
&prcm_base->fclken1_core);
writel(readl(&prcm_base->iclken1_core) |
EN_MMC1 | EN_MMC2 | EN_MMC3,
&prcm_base->iclken1_core);
#endif
#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
/* PBIAS config needed for MMC1 only */
if (mmc->block_dev.devnum == 0)
vmmc_pbias_config(LDO_VOLT_3V0);
#endif
return 0;
}
/******************************************************************************
* prcm_init() - inits clocks for PRCM as defined in clocks.h
* called from SRAM, or Flash (using temp SRAM stack).
*****************************************************************************/
void prcm_init(void)
{
u32 osc_clk = 0, sys_clkin_sel;
u32 clk_index, sil_index = 0;
struct prm *prm_base = (struct prm *)PRM_BASE;
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/*
* Gauge the input clock speed and find out the sys_clkin_sel
* value corresponding to the input clock.
*/
osc_clk = get_osc_clk_speed();
get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
/* set input crystal speed */
sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
/* If the input clock is greater than 19.2M always divide/2 */
if (sys_clkin_sel > 2) {
/* input clock divider */
sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
clk_index = sys_clkin_sel / 2;
} else {
/* input clock divider */
sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
clk_index = sys_clkin_sel;
}
if (get_cpu_family() == CPU_OMAP36XX) {
/* Unlock MPU DPLL (slows things down, and needed later) */
sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
dpll3_init_36xx(0, clk_index);
dpll4_init_36xx(0, clk_index);
dpll5_init_34xx(0, clk_index);
iva_init_36xx(0, clk_index);
mpu_init_36xx(0, clk_index);
/* Lock MPU DPLL to set frequency */
sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
} else {
/*
* The DPLL tables are defined according to sysclk value and
* silicon revision. The clk_index value will be used to get
* the values for that input sysclk from the DPLL param table
* and sil_index will get the values for that SysClk for the
* appropriate silicon rev.
*/
if (((get_cpu_family() == CPU_OMAP34XX)
&& (get_cpu_rev() >= CPU_3XX_ES20)) ||
(get_cpu_family() == CPU_AM35XX))
sil_index = 1;
/* Unlock MPU DPLL (slows things down, and needed later) */
sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
dpll3_init_34xx(sil_index, clk_index);
dpll4_init_34xx(sil_index, clk_index);
dpll5_init_34xx(sil_index, clk_index);
if (get_cpu_family() != CPU_AM35XX)
iva_init_34xx(sil_index, clk_index);
mpu_init_34xx(sil_index, clk_index);
/* Lock MPU DPLL to set frequency */
sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
}
/* Set up GPTimers to sys_clk source only */
sr32(&prcm_base->clksel_per, 0, 8, 0xff);
sr32(&prcm_base->clksel_wkup, 0, 1, 1);
sdelay(5000);
}
/**
* initializes cpuinfo-struct
* @param print detection-summary is written to stdout when !=0
*/
void init_cpuinfo(cpu_info_t *cpuinfo,int print)
{
unsigned int i;
char output[_HW_DETECT_MAX_OUTPUT];
/* initialize data structure */
memset(cpuinfo,0,sizeof(cpu_info_t));
strcpy(cpuinfo->architecture,"unknown\0");
strcpy(cpuinfo->vendor,"unknown\0");
strcpy(cpuinfo->model_str,"unknown\0");
cpuinfo->num_cpus = num_cpus();
get_architecture(cpuinfo->architecture, sizeof(cpuinfo->architecture));
get_cpu_vendor(cpuinfo->vendor, sizeof(cpuinfo->vendor));
get_cpu_name(cpuinfo->model_str, sizeof(cpuinfo->model_str));
cpuinfo->family = get_cpu_family();
cpuinfo->model = get_cpu_model();
cpuinfo->stepping = get_cpu_stepping();
cpuinfo->num_cores_per_package = num_cores_per_package();
cpuinfo->num_threads_per_core = num_threads_per_core();
cpuinfo->num_packages = num_packages();
cpuinfo->clockrate = get_cpu_clockrate(1, 0);
/* setup supported feature list*/
if(!strcmp(cpuinfo->architecture,"x86_64")) cpuinfo->features |= X86_64;
if (feature_available("SMT")) cpuinfo->features |= SMT;
if (feature_available("FPU")) cpuinfo->features |= FPU;
if (feature_available("MMX")) cpuinfo->features |= MMX;
if (feature_available("MMX_EXT")) cpuinfo->features |= MMX_EXT;
if (feature_available("SSE")) cpuinfo->features |= SSE;
if (feature_available("SSE2")) cpuinfo->features |= SSE2;
if (feature_available("SSE3")) cpuinfo->features |= SSE3;
if (feature_available("SSSE3")) cpuinfo->features |= SSSE3;
if (feature_available("SSE4.1")) cpuinfo->features |= SSE4_1;
if (feature_available("SSE4.2")) cpuinfo->features |= SSE4_2;
if (feature_available("SSE4A")) cpuinfo->features |= SSE4A;
if (feature_available("ABM")) cpuinfo->features |= ABM;
if (feature_available("POPCNT")) cpuinfo->features |= POPCNT;
if (feature_available("AVX")) cpuinfo->features |= AVX;
if (feature_available("AVX2")) cpuinfo->features |= AVX2;
if (feature_available("FMA")) cpuinfo->features |= FMA;
if (feature_available("FMA4")) cpuinfo->features |= FMA4;
if (feature_available("AES")) cpuinfo->features |= AES;
if (feature_available("AVX512")) cpuinfo->features |= AVX512;
/* determine cache details */
for (i=0; i<(unsigned int)num_caches(0); i++)
{
cpuinfo->Cache_shared[cache_level(0,i)-1]=cache_shared(0,i);
cpuinfo->Cacheline_size[cache_level(0,i)-1]=cacheline_length(0,i);
if (cpuinfo->Cachelevels < (unsigned int)cache_level(0,i)) { cpuinfo->Cachelevels = cache_level(0,i); }
switch (cache_type(0,i))
{
case UNIFIED_CACHE: {
cpuinfo->Cache_unified[cache_level(0,i)-1]=1;
cpuinfo->U_Cache_Size[cache_level(0,i)-1]=cache_size(0,i);
cpuinfo->U_Cache_Sets[cache_level(0,i)-1]=cache_assoc(0,i);
break;
}
case DATA_CACHE: {
cpuinfo->Cache_unified[cache_level(0,i)-1]=0;
cpuinfo->D_Cache_Size[cache_level(0,i)-1]=cache_size(0,i);
cpuinfo->D_Cache_Sets[cache_level(0,i)-1]=cache_assoc(0,i);
break;
}
case INSTRUCTION_CACHE: {
cpuinfo->Cache_unified[cache_level(0,i)-1]=0;
cpuinfo->I_Cache_Size[cache_level(0,i)-1]=cache_size(0,i);
cpuinfo->I_Cache_Sets[cache_level(0,i)-1]=cache_assoc(0,i);
break;
}
default:
break;
}
}
/* print a summary */
if (print)
{
fflush(stdout);
printf("\n system summary:\n");
if(cpuinfo->num_packages) printf(" number of processors: %i\n",cpuinfo->num_packages);
if(cpuinfo->num_cores_per_package) printf(" number of cores per package: %i\n",cpuinfo->num_cores_per_package);
if(cpuinfo->num_threads_per_core) printf(" number of threads per core: %i\n",cpuinfo->num_threads_per_core);
if(cpuinfo->num_cpus) printf(" total number of threads: %i\n",cpuinfo->num_cpus);
printf("\n processor characteristics:\n");
printf(" architecture: %s\n",cpuinfo->architecture);
printf(" vendor: %s\n",cpuinfo->vendor);
printf(" processor-name: %s\n",cpuinfo->model_str);
printf(" model: Family %i, Model %i, Stepping %i\n",cpuinfo->family,cpuinfo->model,cpuinfo->stepping);
printf(" frequency: %llu MHz\n",cpuinfo->clockrate/1000000);
fflush(stdout);
printf(" supported features:\n -");
if(cpuinfo->features&X86_64) printf(" X86_64");
if(cpuinfo->features&FPU) printf(" FPU");
if(cpuinfo->features&MMX) printf(" MMX");
if(cpuinfo->features&MMX_EXT) printf(" MMX_EXT");
if(cpuinfo->features&SSE) printf(" SSE");
if(cpuinfo->features&SSE2) printf(" SSE2");
if(cpuinfo->features&SSE3) printf(" SSE3");
if(cpuinfo->features&SSSE3) printf(" SSSE3");
if(cpuinfo->features&SSE4_1) printf(" SSE4.1");
if(cpuinfo->features&SSE4_2) printf(" SSE4.2");
if(cpuinfo->features&SSE4A) printf(" SSE4A");
if(cpuinfo->features&POPCNT) printf(" POPCNT");
if(cpuinfo->features&AVX) printf(" AVX");
if(cpuinfo->features&AVX2) printf(" AVX2");
if(cpuinfo->features&AVX512) printf(" AVX512");
if(cpuinfo->features&FMA) printf(" FMA");
if(cpuinfo->features&FMA4) printf(" FMA4");
if(cpuinfo->features&AES) printf(" AES");
if(cpuinfo->features&SMT) printf(" SMT");
printf(" \n");
if(cpuinfo->Cachelevels)
{
printf(" Caches:\n");
for(i = 0; i < (unsigned int)num_caches(0); i++)
{
snprintf(output,sizeof(output),"n/a");
if (cache_info(0, i, output, sizeof(output)) != -1) printf(" - %s\n",output);
}
}
}
fflush(stdout);
}
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
unsigned int expansion_id;
twl4030_power_init();
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
printf("Board revision: %d\n", get_board_revision());
switch (get_sdio2_config()) {
case 0:
puts("Tranceiver detected on mmc2\n");
MUX_OVERO_SDIO2_TRANSCEIVER();
break;
case 1:
puts("Direct connection on mmc2\n");
MUX_OVERO_SDIO2_DIRECT();
break;
default:
puts("Unable to detect mmc2 connection type\n");
}
expansion_id = get_expansion_id();
switch (expansion_id) {
case GUMSTIX_SUMMIT:
printf("Recognized Summit expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "dvi");
setenv("expansionname", "summit");
break;
case GUMSTIX_TOBI:
printf("Recognized Tobi expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "dvi");
setenv("expansionname", "tobi");
break;
case GUMSTIX_TOBI_DUO:
printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("expansionname", "tobiduo");
break;
case GUMSTIX_PALO35:
printf("Recognized Palo35 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "lcd35");
setenv("expansionname", "palo35");
break;
case GUMSTIX_PALO43:
printf("Recognized Palo43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "palo43");
break;
case GUMSTIX_CHESTNUT43:
printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "chestnut43");
break;
case GUMSTIX_PINTO:
printf("Recognized Pinto expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_GALLOP43:
printf("Recognized Gallop43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "gallop43");
break;
case GUMSTIX_ALTO35:
printf("Recognized Alto35 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
MUX_ALTO35();
setenv("defaultdisplay", "lcd35");
setenv("expansionname", "alto35");
break;
case GUMSTIX_STAGECOACH:
printf("Recognized Stagecoach expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_THUMBO:
printf("Recognized Thumbo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_TURTLECORE:
printf("Recognized Turtlecore expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_ARBOR43C:
printf("Recognized Arbor43C expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
MUX_ARBOR43C();
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "arbor43c");
break;
case ETTUS_USRP_E:
printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
MUX_USRP_E();
setenv("defaultdisplay", "dvi");
break;
case GUMSTIX_NO_EEPROM:
case GUMSTIX_EMPTY_EEPROM:
puts("No or empty EEPROM on expansion board\n");
MUX_GUMSTIX();
setenv("expansionname", "tobi");
break;
default:
printf("Unrecognized expansion board 0x%08x\n", expansion_id);
break;
}
if (expansion_config.content == 1)
setenv(expansion_config.env_var, expansion_config.env_setting);
omap_die_id_display();
if (get_cpu_family() == CPU_OMAP34XX)
setenv("boardname", "overo");
else
setenv("boardname", "overo-storm");
return 0;
}
/******************************************************************************
* prcm_init() - inits clocks for PRCM as defined in clocks.h
* called from SRAM, or Flash (using temp SRAM stack).
*****************************************************************************/
void prcm_init(void)
{
u32 osc_clk = 0, sys_clkin_sel;
u32 clk_index, sil_index = 0;
struct prm *prm_base = (struct prm *)PRM_BASE;
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/*
* Gauge the input clock speed and find out the sys_clkin_sel
* value corresponding to the input clock.
*/
osc_clk = get_osc_clk_speed();
get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
/* set input crystal speed */
clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
/* If the input clock is greater than 19.2M always divide/2 */
if (sys_clkin_sel > 2) {
/* input clock divider */
clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
clk_index = sys_clkin_sel / 2;
} else {
/* input clock divider */
clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
clk_index = sys_clkin_sel;
}
if (get_cpu_family() == CPU_OMAP36XX) {
/*
* In warm reset conditions on OMAP36xx/AM/DM37xx
* the rom code incorrectly sets the DPLL4 clock
* input divider to /6.5. Section 3.5.3.3.3.2.1 of
* the AM/DM37x TRM explains that the /6.5 divider
* is used only when the input clock is 13MHz.
*
* If the part is in this cpu family *and* the input
* clock *is not* 13 MHz, then reset the DPLL4 clock
* input divider to /1 as it should never set to /6.5
* in this case.
*/
if (sys_clkin_sel != 1) { /* 13 MHz */
/* Bit 8: DPLL4_CLKINP_DIV */
clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
}
/* Unlock MPU DPLL (slows things down, and needed later) */
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
dpll3_init_36xx(0, clk_index);
dpll4_init_36xx(0, clk_index);
dpll5_init_36xx(0, clk_index);
iva_init_36xx(0, clk_index);
mpu_init_36xx(0, clk_index);
/* Lock MPU DPLL to set frequency */
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
} else {
/*
* The DPLL tables are defined according to sysclk value and
* silicon revision. The clk_index value will be used to get
* the values for that input sysclk from the DPLL param table
* and sil_index will get the values for that SysClk for the
* appropriate silicon rev.
*/
if (((get_cpu_family() == CPU_OMAP34XX)
&& (get_cpu_rev() >= CPU_3XX_ES20)) ||
(get_cpu_family() == CPU_AM35XX))
sil_index = 1;
/* Unlock MPU DPLL (slows things down, and needed later) */
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
dpll3_init_34xx(sil_index, clk_index);
dpll4_init_34xx(sil_index, clk_index);
dpll5_init_34xx(sil_index, clk_index);
if (get_cpu_family() != CPU_AM35XX)
iva_init_34xx(sil_index, clk_index);
mpu_init_34xx(sil_index, clk_index);
/* Lock MPU DPLL to set frequency */
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
}
/* Set up GPTimers to sys_clk source only */
setbits_le32(&prcm_base->clksel_per, 0x000000FF);
setbits_le32(&prcm_base->clksel_wkup, 1);
sdelay(5000);
}
/******************************************************************************
* peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
*****************************************************************************/
void per_clocks_enable(void)
{
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* Enable GP2 timer. */
setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */
setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
/* Enable GP9 timer. */
setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */
setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */
setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */
#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clocks */
setbits_le32(&prcm_base->fclken1_core, 0x00002000);
setbits_le32(&prcm_base->iclken1_core, 0x00002000);
/* Enable UART2 clocks */
setbits_le32(&prcm_base->fclken1_core, 0x00004000);
setbits_le32(&prcm_base->iclken1_core, 0x00004000);
/* UART 3 Clocks */
setbits_le32(&prcm_base->fclken_per, 0x00000800);
setbits_le32(&prcm_base->iclken_per, 0x00000800);
#endif
#ifdef CONFIG_OMAP3_GPIO_2
setbits_le32(&prcm_base->fclken_per, 0x00002000);
setbits_le32(&prcm_base->iclken_per, 0x00002000);
#endif
#ifdef CONFIG_OMAP3_GPIO_3
setbits_le32(&prcm_base->fclken_per, 0x00004000);
setbits_le32(&prcm_base->iclken_per, 0x00004000);
#endif
#ifdef CONFIG_OMAP3_GPIO_4
setbits_le32(&prcm_base->fclken_per, 0x00008000);
setbits_le32(&prcm_base->iclken_per, 0x00008000);
#endif
#ifdef CONFIG_OMAP3_GPIO_5
setbits_le32(&prcm_base->fclken_per, 0x00010000);
setbits_le32(&prcm_base->iclken_per, 0x00010000);
#endif
#ifdef CONFIG_OMAP3_GPIO_6
setbits_le32(&prcm_base->fclken_per, 0x00020000);
setbits_le32(&prcm_base->iclken_per, 0x00020000);
#endif
#ifdef CONFIG_SYS_I2C_OMAP34XX
/* Turn on all 3 I2C clocks */
setbits_le32(&prcm_base->fclken1_core, 0x00038000);
setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
#endif
/* Enable the ICLK for 32K Sync Timer as its used in udelay */
setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
if (get_cpu_family() != CPU_AM35XX)
out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
if (get_cpu_family() != CPU_AM35XX) {
out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
}
sdelay(1000);
}
