int FASTCALL ppc_write_effective_word(uint32 addr, uint32 data)
{
PPC_CPU_State* cpu = get_current_cpu();
e500_core_t * current_core = get_current_core();
uint32 p;
int r;
if(addr & 0x3){
//ppc_exception for unalign
}
if (!((r=ppc_effective_to_physical(current_core, addr, PPC_MMU_WRITE, &p)))) {
if(in_ccsr_range(p)){
int offset = p - current_core->get_ccsr_base(cpu->ccsr);
//skyeye_config.mach->mach_io_write_word(&gCPU, offset, data);
skyeye_config_t* config = get_current_config();
config->mach->mach_io_write_word(cpu, offset, data);
//printf("DBG:write to CCSR,value=0x%x,offset=0x%x,pc=0x%x\n", data, offset,current_core->pc);
}
else{
bus_write(32, p, data);
//fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x,ccsr_base=0x%x, ccsr=0x%x\n", __FUNCTION__, p, current_core->pc, GET_CCSR_BASE(gCPU.ccsr), gCPU.ccsr);
//skyeye_exit(-1);
}
}
return r;
}
int ppc_read_effective_byte(uint32 addr, uint8 *result)
{
e500_core_t * current_core = get_current_core();
PPC_CPU_State* cpu = get_current_cpu();
uint32 p;
int r;
if (!(r = ppc_effective_to_physical(current_core, addr, PPC_MMU_READ, &p))) {
//ppc_io_read_byte (¤t_core-> p);
//printf("\nDBG:in %s,addr=0x%x,p=0x%x\n", __FUNCTION__, addr,p);
//printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x\n",current_core->ccsr.ccsr,GET_CCSR_BASE(current_core->ccsr.ccsr));
if(in_ccsr_range(p)){
int offset = p - current_core->get_ccsr_base(cpu->ccsr);
skyeye_config_t* config = get_current_config();
*result = config->mach->mach_io_read_byte(cpu, offset);
//*result = skyeye_config.mach->mach_io_read_byte(&gCPU, offset);
//printf("In %s, offset=0x%x, *result=0x%x\n", __FUNCTION__, offset, *result);
return r;
}
else{
if(bus_read(8, p, result) != 0){
}
//fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, current_core->pc);
//skyeye_exit(-1);
}
}
return r;
}
int FASTCALL ppc_write_effective_byte(uint32 addr, uint8 data)
{
uint32 p;
int r;
e500_core_t* current_core = get_current_core();
PPC_CPU_State* cpu = get_current_cpu();
if (!((r=ppc_effective_to_physical(current_core, addr, PPC_MMU_WRITE, &p)))) {
//ppc_io_write_byte (¤t_core-> p, data);
//printf("DBG:in %s,addr=0x%x,p=0x%x, data=0x%x, pc=0x%x\n", __FUNCTION__, addr,p, data, current_core->pc);
//printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x",current_core->ccsr.ccsr,GET_CCSR_BASE(current_core->ccsr.ccsr));
if(in_ccsr_range(p)){
int offset = p - current_core->get_ccsr_base(cpu->ccsr);
//skyeye_config.mach->mach_io_write_byte(&gCPU, offset, data);
skyeye_config_t* config = get_current_config();
config->mach->mach_io_write_byte(cpu, offset, data);
return r;
//printf("DBG:write to CCSR,value=0x%x,offset=0x%x\n", data, offset);
}
else{
bus_write(8, p, data);
//fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x,ccsr=0x%x\n", __FUNCTION__, p, current_core->pc, gCPU.ccsr);
//skyeye_exit(-1);
}
}
return r;
}
static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
int id = get_current_cpu(s);
return timerblock_read(&s->timerblock[id * 2 + 1], addr, size);
}
static void arm_thiswdog_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
int id = get_current_cpu(s);
timerblock_write(&s->timerblock[id * 2 + 1], addr, value, size);
}
/* Wrapper functions to implement the "read timer/watchdog for
* the current CPU" memory regions.
*/
static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
unsigned size)
{
ARMMPTimerState *s = (ARMMPTimerState *)opaque;
int id = get_current_cpu(s);
return timerblock_read(&s->timerblock[id], addr, size);
}
static void
arm_set_pc (generic_address_t pc)
{
int i;
ARM_CPU_State* cpu = get_current_cpu();
cpu->core[0].Reg[15] = pc;
}
static void arm_thistimer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
ARMMPTimerState *s = (ARMMPTimerState *)opaque;
int id = get_current_cpu(s);
timerblock_write(&s->timerblock[id], addr, value, size);
}
void mpc8560_boot_linux(){
/* Fixme, will move it to skyeye.conf */
set_bootcmd();
/* just for linux boot, so we need to do some map */
setup_boot_map();
PPC_CPU_State* cpu = get_current_cpu();
cpu->ccsr = 0xE0000; /* Just for boot linux */
}
void arm_user_mode_init(generic_arch_t * arch_instance)
{
sky_pref_t *pref = get_skyeye_pref();
if (pref->user_mode_sim)
{
sky_exec_info_t *info = get_skyeye_exec_info();
info->arch_page_size = 0x1000;
info->arch_stack_top = 0x1ffffff0;// + 0x401fe7 - 0xff0; /* arbitrary value */
/* stack initial address specific to architecture may be placed here */
/* we need to mmap the stack space, if we are using skyeye space */
if (info->mmap_access)
{
/* get system stack size */
size_t stacksize = 0;
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_attr_getstacksize(&attr, &stacksize);
if (stacksize > info->arch_stack_top)
{
printf("arch_stack_top is too low\n");
stacksize = info->arch_stack_top;
}
/* Note: Skyeye is occupating 0x400000 to 0x600000 */
/* We do a mmap */
void* ret = mmap( (info->arch_stack_top) - stacksize,
stacksize + 0x1000 , PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
if (ret == MAP_FAILED){
/* ideally, we should find an empty space until it works */
printf("mmap error, stack couldn't be mapped: errno %d\n", errno);
exit(-1);
} else {
memset(ret, '\0', stacksize);
//printf("stack top has been defined at %x size %x\n", (uint32_t) ret + stacksize, stacksize);
//info->arch_stack_top = (uint32_t) ret + stacksize;
}
}
exec_stack_init();
ARM_CPU_State* cpu = get_current_cpu();
arm_core_t* core = &cpu->core[0];
uint32_t sp = info->initial_sp;
core->Cpsr = 0x10; /* User mode */
/* FIXME: may need to add thumb */
core->Reg[13] = sp;
core->Reg[10] = info->start_data;
core->Reg[0] = 0;
bus_read(32, sp + 4, &(core->Reg[1]));
bus_read(32, sp + 8, &(core->Reg[2]));
}
}
static void
std8250_io_do_cycle (void * state)
{
const int core_id = 0; /* currently, we only send uart interrupt to cpu0 */
PPC_CPU_State* cpu = get_current_cpu();
e500_core_t * core = &cpu->core[0];
mpc8572_io_t *io = &mpc8572_io;
std_16550_uart_t *uart = &io->uart[0];
/*
if(!(core->msr & 0x8000))
return;
*/
if (uart->iir & 0x1) {
if (uart->ier & 0x2) { /* THREI enabled */
//printf("In %s, THR interrupt\n", __FUNCTION__);
uart->iir = (uart->iir & 0xf0) | 0x2;
uart->lsr |= 0x60;
}
if (uart->ier & 0x1) { /* RDAI enabled */
struct timeval tv;
unsigned char c;
tv.tv_sec = 0;
tv.tv_usec = 0;
if (skyeye_uart_read (-1, &c, 1, &tv, NULL) > 0) {
uart->rbr = (int) c;
//printf("SKYEYE: io_do_cycle set ffiir or 04, now %x\n",pxa250_io.ffiir);
uart->lsr |= 0x01; //Data ready
uart->iir = (uart->iir & 0xf0) | 0x4;
}
}
}
if ((!(io->mpic.iivpr[UART_IRQ] & 0x80000000) && (core->msr & 0x8000)
&& !(core->ipr & 1 << UART_IRQ))) {
//if(!(io->mpic.iivpr[UART_IRQ] & 0x80000000)){
if ((!(uart->iir & 0x1)) && (uart->ier & 0x3)
) {
//printf ("In %s,uart int triggered. ier=0x%x\n", __FUNCTION__, uart->ier);
core->ipr |= (1 << UART_IRQ);
io->mpic.iivpr[UART_IRQ] |= 0x40000000; /* set activity bit in vpr */
io->pic_percpu.iack[core_id] =
(io->pic_percpu.
iack[core_id] & 0xFFFF0000) | (io->mpic.
ipivpr
[UART_IRQ] &
0xFFFF);
io->pic_percpu.iack[core_id] = 0x2a;
//printf("In %s, ack=0x%x\n", __FUNCTION__, io->pic_percpu.iack[core_id]);
core->ipi_flag = 1; /* we need to inform the core that npc is changed to exception vector */
ppc_exception (core, EXT_INT, 0, 0);
}
}
}
static uint32_t
mpc8572_io_read_halfword (void *state, uint32_t offset)
{
PPC_CPU_State* cpu = get_current_cpu();
e500_core_t *current_core = get_current_core();
mpc8572_io_t *io = &mpc8572_io;
//int offset = p - GET_CCSR_BASE (io->ccsr.ccsr);
//printf("DBG:read CCSR,offset=0x%x,pc=0x%x\n", offset, current_core->pc);
if (offset >= 0x919C0 && offset <= 0x919E0) {
switch (offset) {
default:
/*
fprintf (stderr,
"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
*/
skyeye_exit (-1);
}
}
if (offset >= 0xE0000 && offset <= 0xE0020) {
switch (offset) {
case 0xE0000:
return io->por_conf.porpllsr;
default:
/*
fprintf (stderr,
"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
*/
skyeye_exit (-1);
}
}
switch (offset) {
case 0x0:
return cpu->ccsr;
case 0x90C80:
return io->sccr;
case 0x8004:
return io->pci_cfg.cfg_data;
case 0x8006:
return io->pci_cfg.cfg_data;
default:
fprintf (stderr,
"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
return 0;
//skyeye_exit(-1);
}
}
static void
arm_step_once ()
{
int i;
machine_config_t* mach = get_current_mach();
ARM_CPU_State* cpu = get_current_cpu();
/* workaround boot sequence for dual core, we need the first core initialize some variable for second core. */
arm_core_t* core;
for(i = 0; i < cpu->core_num; i++ ){
core = &cpu->core[i];
/* if CPU1_EN is set? */
per_cpu_step(core);
}
/* for peripheral */
mach->mach_io_do_cycle(cpu);
}
int FASTCALL ppc_read_effective_word(uint32 addr, uint32 *result)
{
e500_core_t* current_core = get_current_core();
PPC_CPU_State* cpu = get_current_cpu();
uint32 p;
int r;
if (!(r = ppc_effective_to_physical(current_core, addr, PPC_MMU_READ, &p))) {
if(in_ccsr_range(p)){
skyeye_config_t *config = get_current_config();
*result = config->mach->mach_io_read_word(cpu, (p - current_core->get_ccsr_base(cpu->ccsr)));
}
else{
if(bus_read(32, p, result) != 0){
}
}
}
return r;
}
int FASTCALL ppc_read_effective_half(uint32 addr, uint16 *result)
{
e500_core_t * current_core = get_current_core();
PPC_CPU_State* cpu = get_current_cpu();
uint32 p;
int r;
if (!(r = ppc_effective_to_physical(current_core, addr, PPC_MMU_READ, &p))) {
//ppc_io_read_halfword(¤t_core-> p);
//printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x\n",current_core->ccsr.ccsr,GET_CCSR_BASE(current_core->ccsr.ccsr));
if(in_ccsr_range(p)){
//*result = skyeye_config.mach->mach_io_read_halfword(&gCPU, (p - GET_CCSR_BASE(gCPU.ccsr)));
skyeye_config_t* config = get_current_config();
*result = config->mach->mach_io_read_halfword(cpu, (p - current_core->get_ccsr_base(cpu->ccsr)));
}
else{
if(bus_read(16, p, result) != 0){
}
//fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, current_core->pc);
//skyeye_exit(-1);
}
}
return r;
}
void check_stack(void)
{
__thread cpu_p pcpu = get_current_cpu();
extern ulong init_stack_top[];
extern void switchtrapret(void);
ulong min;
ulong max;
ulong rbp = read_rbp();
if (is_bp_cpu(pcpu)) {
max = (ulong) init_stack_top;
min = max - 4 * 4096;
printk("BP stack:min:%lx-max:%lx,irqret:%lx,rbp:%lx\n", min, max,
switchtrapret, rbp);
}
else {
min = (uint64) per_cpu_ptr(&init_stack, pcpu->cpu);
max = min + sizeof(init_stack);
printk("AP stack:min:%lx-max:%lx\n", min, max);
}
ulong *p;
int stacknr = 0;
p = (ulong *) rbp;
while ((ulong) p >= min && (ulong) p < max && ++stacknr < 50) {
if ((ulong) (switchtrapret) == *(p + 1)) {
printk("irq:%lx,rbp:%lx,rip:%lx\n", *(p + 1), p, *(p + 19));
}
else
printk("%lx,rbp:%lx\n", *(p + 1), p);
p = (ulong *) * p;
}
}
static void s5l8930_iop_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
s5l8930_iop_s *s = (s5l8930_iop_s *)opaque;
//fprintf(stderr, "%s:%s: offset 0x%08x value 0x%08x isARM7_CPU 0x%p\n", __FUNCTION__, s->name, offset, value, get_current_cpu());
//cpu_synchronize_all_states();
switch(offset) {
case 0x18:
case 0x1c:
case 0x24:
return;
case 0x100:
if(value & 0x10) { /* Stop CPU ? */
s->status |= 0x2;
break;
}
if(value & 0x1) {
fprintf(stderr, "switching cpu state to start IOP processing @ address 0x%08x\n", s->startaddr);
cpu_interrupt(s->s5l8930env, CPU_INTERRUPT_HALT);
//pause_all_vcpus();
//switch_iop_mode(s->env, ARM_MODE_IOP);
run_on_cpu(s->iopenv, do_iop_run, s);
//s->iopenv->regs[15] = s->startaddr;
//resume_all_vcpus();
}
s->status = value;
break;
case 0x110:
s->startaddr = value;
break;
default:
fprintf(stderr, "%s:%s: UNKNOWN offset 0x%08x value 0x%08x isARM7_CPU 0x%p\n", __FUNCTION__, s->name, offset, value, get_current_cpu());
break;
}
}
int HT_SetAffinity()
{
unsigned long mask;
pid_t pid;
int result=1;
int cpu_count, i, j, k, cpuid;
pid=getpid();
tst_resm(TINFO, "Set affinity through system call.\n");
cpu_count=get_cpu_count();
if(cpu_count==0)
{
return 0;
}
else if(cpu_count>32)
cpu_count=32;
for(i=0, mask=0x1;i<cpu_count;i++, mask=mask<<1)
{
tst_resm(TINFO, "Set test process affinity.");
printf("mask: %x\n",mask);
sched_setaffinity(pid, sizeof(unsigned long), &mask);
for(j=0;j<10;j++)
{
for(k=0;k<10;k++)
{
if(fork()==0)
{
system("ps > /dev/null");
exit(0);
}
}
sleep(1);
if(get_current_cpu(pid)!=i)
break;
}
if(j<10)
{
tst_resm(TINFO, "...Error\n");
result=0;
}
else
tst_resm(TINFO, "...OK\n");
}
for(i=0, mask=0x3;i<cpu_count-1;i++, mask=mask<<1)
{
tst_resm(TINFO, "Set test process affinity.");
printf("mask: %x\n",mask);
sched_setaffinity(pid, sizeof(unsigned long), &mask);
for(j=0;j<10;j++)
{
for(k=0;k<10;k++)
{
if(fork()==0)
{
system("ps > /dev/null");
exit(0);
}
}
sleep(1);
cpuid=get_current_cpu(pid);
if(cpuid!=i&&cpuid!=i+1)
break;
}
if(j<10)
{
tst_resm(TINFO, "...Error\n");
result=0;
}
else
tst_resm(TINFO, "...OK\n");
}
if(result)
return 1;
else
return 0;
}
static uint32_t
mpc8572_io_read_word (void *state, uint32_t offset)
{
PPC_CPU_State* cpu = get_current_cpu();
e500_core_t *current_core = get_current_core();
mpc8572_io_t *io = &mpc8572_io;
//printf("DBG:in %s,read CCSR,offset=0x%x,pc=0x%x\n", __FUNCTION__, offset, current_core->pc);
if (offset >= 0x919C0 && offset <= 0x919E0) {
switch (offset) {
default:
/*
fprintf (stderr,
"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
*/
skyeye_exit (-1);
}
}
if (offset >= 0x2000 && offset <= 0x2E58) {
switch (offset) {
case 0x2E44:
return io->ddr_ctrl.err_disable;
default:
/*
fprintf (stderr,
"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
*/
skyeye_exit (-1);
}
}
/* PIC Global register */
if (offset >= 0x40000 && offset <= 0x7FFF0) {
#if 0
int tmp;
if (offset == 0x41020) {
/* source attribute register for DMA0 */
//printf("In %s,read gcr=0x%x\n", __FUNCTION__, *result);
*result = io->pic_global.gcr & ~0x80000000; /* we clear RST bit after finish initialization of PIC */
//*result = io->pic_global.gcr & ~0x1;
printf ("In %s,read gcr=0x%x, pc=0x%x\n",
__FUNCTION__, *result, current_core->pc);
return r;
}
r = e500_mpic_read_word (offset, &tmp);
*result = tmp;
return r;
#endif
switch (offset) {
case 0x400a0:
return io->pic_global.iack;
case 0x41000:
return io->pic_global.frr; /* according to MPC8572 manual */
case 0x41020:
/* source attribute register for DMA0 */
//printf("In %s,read gcr=0x%x\n", __FUNCTION__, *result);
return io->pic_global.gcr & ~0x80000000; /* we clear RST bit after finish initialization of PIC */
//printf("In %s,read gcr=0x%x, pc=0x%x\n", __FUNCTION__, *result, current_core->pc);
case 0x410a0:
case 0x410b0:
case 0x410c0:
case 0x410d0:
return io->mpic.ipivpr[(offset - 0x410a0) >> 4];
case 0x410e0:
return io->pic_global.svr;
case 0x410f0:
return io->pic_global.tfrr;
case 0x41120:
return io->pic_global.gtvpr0;
case 0x41160:
return io->pic_global.gtvpr1;
case 0x41170:
return io->pic_global.gtdr1;
case 0x411a0:
return io->pic_global.gtvpr2;
case 0x411B0:
return io->pic_global.gtdr2;
case 0x411E0:
return io->pic_global.gtvpr3;
default:
/*
fprintf(stderr,"in %s, error when read global.offset=0x%x, \
pc=0x%x\n",__FUNCTION__, offset, current_core->pc);
return r;
*/
break;
//skyeye_exit(-1);
}
if (offset >= 0x50000 && offset <= 0x50170) {
int index = (offset - 0x50000) >> 4;
if (index & 0x1)
return io->pic_ram.eidr[index >> 1];
else
return io->pic_ram.eivpr[index >> 1];
static uint32_t
mpc8572_io_read_byte (void *state, uint32_t offset)
{
PPC_CPU_State* cpu = get_current_cpu();
mpc8572_io_t *io = &mpc8572_io;
if (offset >= 0x919C0 && offset <= 0x919E0) {
switch (offset) {
default:
/*
fprintf (stderr,
"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",
__FUNCTION__, offset, core->pc);
*/
skyeye_exit (-1);
}
}
if (offset >= 0xE0000 && offset <= 0xE0020) {
switch (offset) {
case 0xE0000:
return io->por_conf.porpllsr;
default:
/*
fprintf (stderr,
"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
*/
skyeye_exit (-1);
}
}
switch (offset) {
case 0x0:
return cpu->ccsr;
case 0x90C80:
return io->sccr;
case 0x300C:
return io->i2c_reg.i2csr;
case 0x8006:
return io->pci_cfg.cfg_data;
case 0x4500:
io->uart[0].lsr &= ~0x01;
return io->uart[0].rbr;
case 0x4501:
//printf("In %s,read offset=0x%x,pc=0x%x\n", __FUNCTION__, offset, current_core->pc);
if (io->uart[0].lcr & 0x80)
return io->uart[0].dmb;
else
return io->uart[0].ier;
case 0x4502:
if (io->uart[0].lcr & 0x80)
return io->uart[0].afr;
else {
uint32_t tmp = io->uart[0].iir;
io->uart[0].iir = (io->uart[0].iir & 0xf0) | 0x1;
//printf("In %s,read offset=0x%x,iir=0x%x, pc=0x%x\n", __FUNCTION__, offset, tmp, current_core->pc);
return tmp;
}
case 0x4503:
//printf("In %s,read offset=0x%x\n", __FUNCTION__, offset);
return io->uart[0].lcr;
case 0x4504:
//printf("In %s,read offset=0x%x\n", __FUNCTION__, offset);
return io->uart[0].mcr;
case 0x4505:
return io->uart[0].lsr; /* THRE */
case 0x4506:
return io->uart[0].msr;
case 0x4507:
return io->uart[0].scr;
case 0x4600:
return io->uart[1].rbr;
case 0x4601:
//printf("In %s,read offset=0x%x,pc=0x%x\n", __FUNCTION__, offset, current_core->pc);
if (io->uart[1].lcr & 0x80)
return io->uart[1].dmb;
else
return io->uart[1].ier;
case 0x4602:
if (io->uart[1].lcr & 0x80)
return io->uart[1].afr;
else
return io->uart[1].iir;
case 0x4603:
//printf("In %s,read offset=0x%x\n", __FUNCTION__, offset);
return io->uart[1].lcr;
case 0x4604:
//printf("In %s,read offset=0x%x\n", __FUNCTION__, offset);
return io->uart[1].mcr;
case 0x4607:
return io->uart[1].scr;
default:
/*
fprintf (stderr,
"in %s, error when read CCSR. offset=0x%x, pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
*/
return 0;
//skyeye_exit(-1);
}
}
static exception_t arm_set_register_by_id(int id, uint32 value){
ARM_CPU_State* cpu = get_current_cpu();
cpu->core[0].Reg[id] = value;
return No_exp;
}
/**
* @brief get the current pc for a specified core
*
* @return the current step count for the core
*/
static uint32 arm_get_step(){
ARM_CPU_State* cpu = get_current_cpu();
return cpu->core[0].step;
}
static uint32_t
arm_get_pc(){
ARM_CPU_State* cpu = get_current_cpu();
return cpu->core[0].Reg[15];
}
static uint32_t s5l8930_iop_read(void *opaque, target_phys_addr_t offset)
{
s5l8930_iop_s *s = (s5l8930_iop_s *)opaque;
fprintf(stderr, "%s:%s: offset 0x%08x isARM7_CPU 0x%p\n", __FUNCTION__, s->name, offset, get_current_cpu());
switch(offset) {
case 0x18:
case 0x1c:
case 0x24:
return 0;
case 0x100:
return s->status;
case 0x110:
return s->startaddr;
default:
fprintf(stderr, "%s:%s: UNKNOWN offset 0x%08x isARM7_CPU 0x%p\n", __FUNCTION__, s->name, offset, get_current_cpu());
break;
}
return 0;
}
static uint32 arm_get_regval_by_id(int id){
/* we return the reg value of core 0 by default */
int core_id = 0;
ARM_CPU_State* cpu = get_current_cpu();
}
//#define DEFAULT_CCSR_MEM 0xF8000000
//#define CCSR_MEM_SIZE 0x100000
//#define GET_CCSR_BASE(reg)(((reg >> 8)&0xFFFF) << 16)
static inline bool_t in_ccsr_range(uint32 p){
PPC_CPU_State* cpu = get_current_cpu();
e500_core_t* current_core = get_current_core();
return (p >= current_core->get_ccsr_base(cpu->ccsr)) && (p < (current_core->get_ccsr_base(cpu->ccsr) + current_core->ccsr_size));
}
