int picos_to_clk(int picos) { int clks; clks = picos / (2000000000 / (get_ddr_freq(0) / 1000)); if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) { clks++; } return clks; }
phys_size_t fixed_sdram(void) { int i; char buf[32]; fsl_ddr_cfg_regs_t ddr_cfg_regs; phys_size_t ddr_size; ulong ddr_freq, ddr_freq_mhz; ddr_freq = get_ddr_freq(0); ddr_freq_mhz = ddr_freq / 1000000; printf("Configuring DDR for %s MT/s data rate\n", strmhz(buf, ddr_freq)); for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, sizeof(ddr_cfg_regs)); break; } } if (fixed_ddr_parm_0[i].max_freq == 0) panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, ddr_freq)); ddr_size = (phys_size_t)2048 * 1024 * 1024; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); return ddr_size; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num > 1) { printf("Wrong parameter for controller number %d", ctrl_num); return; } if (!pdimm->n_ranks) return; if (popts->registered_dimm_en) pbsp = rdimms[ctrl_num]; else pbsp = udimms[ctrl_num]; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found " "for data rate %lu MT/s!\n" "Trying to use the highest speed (%u) parameters\n", ddr_freq, pbsp_highest->datarate_mhz_high); popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twot_en = pbsp->force_2t; } else { panic("DIMM is not supported by this board"); } found: /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const board_specific_parameters_t *pbsp = &(board_specific_parameters[ctrl_num][0]); u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / sizeof(board_specific_parameters[0][0]); u32 i; ulong ddr_freq; /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If * there are two dimms in the controller, set odt_rd_cfg to 3 and * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 1; } /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; for (i = 0; i < num_params; i++) { if (ddr_freq >= pbsp->datarate_mhz_low && ddr_freq <= pbsp->datarate_mhz_high && pdimm->n_ranks == pbsp->n_ranks) { popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twoT_en = pbsp->force_2T; break; } pbsp++; } if (i == num_params) { printf("Warning: board specific timing not found " "for data rate %lu MT/s!\n", ddr_freq); } /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; popts->wrlvl_en = 1; /* Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xa; popts->wrlvl_start = 0x8; /* Rtt and Rtt_WR override */ popts->rtt_override = 1; popts->rtt_override_value = DDR3_RTT_120_OHM; popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ }
phys_size_t fixed_sdram(void) { int i; char buf[32]; fsl_ddr_cfg_regs_t ddr_cfg_regs; phys_size_t ddr_size; unsigned int lawbar1_target_id; ulong ddr_freq, ddr_freq_mhz; ddr_freq = get_ddr_freq(0); ddr_freq_mhz = ddr_freq / 1000000; printf("Configuring DDR for %s MT/s data rate\n", strmhz(buf, ddr_freq)); for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, sizeof(ddr_cfg_regs)); break; } } if (fixed_ddr_parm_0[i].max_freq == 0) panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, ddr_freq)); ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); /* * setup laws for DDR. If not interleaving, presuming half memory on * DDR1 and the other half on DDR2 */ if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_INTRLV) < 0) { printf("ERROR setting Local Access Windows for DDR\n"); return 0; } } else { lawbar1_target_id = LAW_TRGT_IF_DDR_1; if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, lawbar1_target_id) < 0) { printf("ERROR setting Local Access Windows for DDR\n"); return 0; } } return ddr_size; }
phys_size_t fixed_sdram (void) { char buf[32]; fsl_ddr_cfg_regs_t ddr_cfg_regs; size_t ddr_size; struct cpu_type *cpu; ulong ddr_freq, ddr_freq_mhz; cpu = gd->arch.cpu; /* P1020 and it's derivatives support max 32bit DDR width */ if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); } else { ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #if defined(CONFIG_SYS_RAMBOOT) return ddr_size; #endif ddr_freq = get_ddr_freq(0); ddr_freq_mhz = ddr_freq / 1000000; printf("Configuring DDR for %s MT/s data rate\n", strmhz(buf, ddr_freq)); if(ddr_freq_mhz <= 400) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs)); else if(ddr_freq_mhz <= 533) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs)); else if(ddr_freq_mhz <= 667) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs)); else if(ddr_freq_mhz <= 800) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs)); else panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, ddr_freq)); /* P1020 and it's derivatives support max 32bit DDR width */ if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; ddr_cfg_regs.cs[0].bnds = 0x0000001F; } fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1); return ddr_size; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const board_specific_parameters_t *pbsp = &(board_specific_parameters[ctrl_num][0]); u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / sizeof(board_specific_parameters[0][0]); u32 i; ulong ddr_freq; /* set odt_rd_cfg and odt_wr_cfg. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 1; } /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; for (i = 0; i < num_params; i++) { if (ddr_freq >= pbsp->datarate_mhz_low && ddr_freq <= pbsp->datarate_mhz_high && pdimm->n_ranks == pbsp->n_ranks) { popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twoT_en = pbsp->force_2T; } pbsp++; } /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 1; /* * For wake up arp feature, we need enable auto self refresh */ popts->auto_self_refresh_en = 1; popts->sr_it = 0xb; }
/* * Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) { int i; char buf[32]; fsl_ddr_cfg_regs_t ddr_cfg_regs; phys_size_t ddr_size; ulong ddr_freq, ddr_freq_mhz; struct cpu_type *cpu; #if defined(CONFIG_SYS_RAMBOOT) return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; #endif ddr_freq = get_ddr_freq(0); ddr_freq_mhz = ddr_freq / 1000000; printf("Configuring DDR for %s MT/s data rate\n", strmhz(buf, ddr_freq)); for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, sizeof(ddr_cfg_regs)); break; } } if (fixed_ddr_parm_0[i].max_freq == 0) panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, ddr_freq)); cpu = gd->cpu; /* P1014 and it's derivatives support max 16bit DDR width */ if (cpu->soc_ver == SVR_P1014) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1; ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000; ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000; }
/* * Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) { int i; char buf[32]; fsl_ddr_cfg_regs_t ddr_cfg_regs; phys_size_t ddr_size; ulong ddr_freq, ddr_freq_mhz; ddr_freq = get_ddr_freq(0); ddr_freq_mhz = ddr_freq / 1000000; printf("Configuring DDR for %s MT/s data rate\n", strmhz(buf, ddr_freq)); for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, sizeof(ddr_cfg_regs)); break; } } if (fixed_ddr_parm_0[i].max_freq == 0) panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, ddr_freq)); ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { printf("ERROR setting Local Access Windows for DDR\n"); return 0; } return ddr_size; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; unsigned long ddr_freq; unsigned int i; if (ctrl_num) { printf("Wrong parameter for controller number %d", ctrl_num); return; } if (!pdimm->n_ranks) return; /* set odt_rd_cfg and odt_wr_cfg. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 1; } pbsp = dimm0; /* * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twoT_en = pbsp->force_2T; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found " "for data rate %lu MT/s!\n" "Trying to use the highest speed (%u) parameters\n", ddr_freq, pbsp_highest->datarate_mhz_high); popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twoT_en = pbsp->force_2T; } else { panic("DIMM is not supported by this board"); } found: popts->half_strength_driver_enable = 1; /* Per AN4039, enable ZQ calibration. */ popts->zq_en = 1; /* * For wake-up on ARP, we need auto self refresh enabled */ popts->auto_self_refresh_en = 1; popts->sr_it = 0xb; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const board_specific_parameters_t *pbsp = &(board_specific_parameters[ctrl_num][0]); u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / sizeof(board_specific_parameters[0][0]); u32 i; ulong ddr_freq; /* * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If * there are two dimms in the controller, set odt_rd_cfg to 3 and * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i&1) { /* odd CS */ popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 0; } else { /* even CS */ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 4; } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { popts->cs_local_opts[i].odt_rd_cfg = 3; popts->cs_local_opts[i].odt_wr_cfg = 3; } } } /* * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; for (i = 0; i < num_params; i++) { if (ddr_freq >= pbsp->datarate_mhz_low && ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->twot_en = 0; break; } pbsp++; } if (i == num_params) { printf("Warning: board specific timing not found " "for data rate %lu MT/s!\n", ddr_freq); } /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; /* * Enable on-die termination. * From the Micron Technical Node TN-41-04, RTT_Nom should typically * be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR * is handled in the Freescale DDR3 driver. Set RTT_Nom here. */ popts->rtt_override = 1; popts->rtt_override_value = 3; }
unsigned int populate_memctl_options(int all_dimms_registered, memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { unsigned int i; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; #if defined(CONFIG_SYS_FSL_DDR3) || \ defined(CONFIG_SYS_FSL_DDR2) || \ defined(CONFIG_SYS_FSL_DDR4) const struct dynamic_odt *pdodt = odt_unknown; #endif ulong ddr_freq; /* * Extract hwconfig from environment since we have not properly setup * the environment but need it for ddr config params */ if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; #if defined(CONFIG_SYS_FSL_DDR3) || \ defined(CONFIG_SYS_FSL_DDR2) || \ defined(CONFIG_SYS_FSL_DDR4) /* Chip select options. */ #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) switch (pdimm[0].n_ranks) { case 1: pdodt = single_S; break; case 2: pdodt = single_D; break; case 4: pdodt = single_Q; break; } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) switch (pdimm[0].n_ranks) { #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE case 4: pdodt = single_Q; if (pdimm[1].n_ranks) printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n"); break; #endif case 2: switch (pdimm[1].n_ranks) { case 2: pdodt = dual_DD; break; case 1: pdodt = dual_DS; break; case 0: pdodt = dual_D0; break; } break; case 1: switch (pdimm[1].n_ranks) { case 2: pdodt = dual_SD; break; case 1: pdodt = dual_SS; break; case 0: pdodt = dual_S0; break; } break; case 0: switch (pdimm[1].n_ranks) { case 2: pdodt = dual_0D; break; case 1: pdodt = dual_0S; break; } break; } #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */ #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */ /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { #if defined(CONFIG_SYS_FSL_DDR3) || \ defined(CONFIG_SYS_FSL_DDR2) || \ defined(CONFIG_SYS_FSL_DDR4) popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr; #else popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; #endif popts->cs_local_opts[i].auto_precharge = 0; } /* Pick interleaving mode. */ /* * 0 = no interleaving * 1 = interleaving between 2 controllers */ popts->memctl_interleaving = 0; /* * 0 = cacheline * 1 = page * 2 = (logical) bank * 3 = superbank (only if CS interleaving is enabled) */ popts->memctl_interleaving_mode = 0; /* * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl * 1: page: bit to the left of the column bits selects the memctl * 2: bank: bit to the left of the bank bits selects the memctl * 3: superbank: bit to the left of the chip select selects the memctl * * NOTE: ba_intlv (rank interleaving) is independent of memory * controller interleaving; it is only within a memory controller. * Must use superbank interleaving if rank interleaving is used and * memory controller interleaving is enabled. */ /* * 0 = no * 0x40 = CS0,CS1 * 0x20 = CS2,CS3 * 0x60 = CS0,CS1 + CS2,CS3 * 0x04 = CS0,CS1,CS2,CS3 */ popts->ba_intlv_ctl = 0; /* Memory Organization Parameters */ popts->registered_dimm_en = all_dimms_registered; /* Operational Mode Paramters */ /* Pick ECC modes */ popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */ #ifdef CONFIG_DDR_ECC if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) { if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf)) popts->ecc_mode = 1; } else popts->ecc_mode = 1; #endif popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ /* * Choose DQS config * 0 for DDR1 * 1 for DDR2 */ #if defined(CONFIG_SYS_FSL_DDR1) popts->dqs_config = 0; #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) popts->dqs_config = 1; #endif /* Choose self-refresh during sleep. */ popts->self_refresh_in_sleep = 1; /* Choose dynamic power management mode. */ popts->dynamic_power = 0; /* * check first dimm for primary sdram width * presuming all dimms are similar * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) if (pdimm[0].n_ranks != 0) { if ((pdimm[0].data_width >= 64) && \ (pdimm[0].data_width <= 72)) popts->data_bus_width = 0; else if ((pdimm[0].data_width >= 32) || \ (pdimm[0].data_width <= 40)) popts->data_bus_width = 1; else { panic("Error: data width %u is invalid!\n", pdimm[0].data_width); } } #else if (pdimm[0].n_ranks != 0) { if (pdimm[0].primary_sdram_width == 64) popts->data_bus_width = 0; else if (pdimm[0].primary_sdram_width == 32) popts->data_bus_width = 1; else if (pdimm[0].primary_sdram_width == 16) popts->data_bus_width = 2; else { panic("Error: primary sdram width %u is invalid!\n", pdimm[0].primary_sdram_width); } } #endif popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0; /* Choose burst length. */ #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) #if defined(CONFIG_E500MC) popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ #else if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { /* 32-bit or 16-bit bus */ popts->otf_burst_chop_en = 0; popts->burst_length = DDR_BL8; } else { popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */ popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ } #endif #else popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ #endif /* Choose ddr controller address mirror mode */ #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { if (pdimm[i].n_ranks) { popts->mirrored_dimm = pdimm[i].mirrored_dimm; break; } } #endif /* Global Timing Parameters. */ debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num)); /* Pick a caslat override. */ popts->cas_latency_override = 0; popts->cas_latency_override_value = 3; if (popts->cas_latency_override) { debug("using caslat override value = %u\n", popts->cas_latency_override_value); } /* Decide whether to use the computed derated latency */ popts->use_derated_caslat = 0; /* Choose an additive latency. */ popts->additive_latency_override = 0; popts->additive_latency_override_value = 3; if (popts->additive_latency_override) { debug("using additive latency override value = %u\n", popts->additive_latency_override_value); } /* * 2T_EN setting * * Factors to consider for 2T_EN: * - number of DIMMs installed * - number of components, number of active ranks * - how much time you want to spend playing around */ popts->twot_en = 0; popts->threet_en = 0; /* for RDIMM, address parity enable */ popts->ap_en = 1; /* * BSTTOPRE precharge interval * * Set this to 0 for global auto precharge * The value of 0x100 has been used for DDR1, DDR2, DDR3. * It is not wrong. Any value should be OK. The performance depends on * applications. There is no one good value for all. */ popts->bstopre = 0x100; /* * Window for four activates -- tFAW * * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only * FIXME: varies depending upon number of column addresses or data * FIXME: width, was considering looking at pdimm->primary_sdram_width */ #if defined(CONFIG_SYS_FSL_DDR1) popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1); #elif defined(CONFIG_SYS_FSL_DDR2) /* * x4/x8; some datasheets have 35000 * x16 wide columns only? Use 50000? */ popts->tfaw_window_four_activates_ps = 37500; #else popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps; #endif popts->zq_en = 0; popts->wrlvl_en = 0; #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) /* * due to ddr3 dimm is fly-by topology * we suggest to enable write leveling to * meet the tQDSS under different loading. */ popts->wrlvl_en = 1; popts->zq_en = 1; popts->wrlvl_override = 0; #endif /* * Check interleaving configuration from environment. * Please refer to doc/README.fsl-ddr for the detail. * * If memory controller interleaving is enabled, then the data * bus widths must be programmed identically for all memory controllers. * * Attempt to set all controllers to the same chip select * interleaving mode. It will do a best effort to get the * requested ranks interleaved together such that the result * should be a subset of the requested configuration. * * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving * with 256 Byte is enabled. */ #if (CONFIG_NUM_DDR_CONTROLLERS > 1) if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B ; #else goto done; #endif if (pdimm[0].n_ranks == 0) { printf("There is no rank on CS0 for controller %d.\n", ctrl_num); popts->memctl_interleaving = 0; goto done; } popts->memctl_interleaving = 1; #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING; popts->memctl_interleaving = 1; debug("256 Byte interleaving\n"); #else /* * test null first. if CONFIG_HWCONFIG is not defined * hwconfig_arg_cmp returns non-zero */ if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "null", buf)) { popts->memctl_interleaving = 0; debug("memory controller interleaving disabled.\n"); } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "cacheline", buf)) { popts->memctl_interleaving_mode = ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 0 : FSL_DDR_CACHE_LINE_INTERLEAVING; popts->memctl_interleaving = ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 0 : 1; } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "page", buf)) { popts->memctl_interleaving_mode = ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 0 : FSL_DDR_PAGE_INTERLEAVING; popts->memctl_interleaving = ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 0 : 1; } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "bank", buf)) { popts->memctl_interleaving_mode = ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 0 : FSL_DDR_BANK_INTERLEAVING; popts->memctl_interleaving = ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 0 : 1; } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "superbank", buf)) { popts->memctl_interleaving_mode = ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 0 : FSL_DDR_SUPERBANK_INTERLEAVING; popts->memctl_interleaving = ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 0 : 1; #if (CONFIG_NUM_DDR_CONTROLLERS == 3) } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "3way_1KB", buf)) { popts->memctl_interleaving_mode = FSL_DDR_3WAY_1KB_INTERLEAVING; } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "3way_4KB", buf)) { popts->memctl_interleaving_mode = FSL_DDR_3WAY_4KB_INTERLEAVING; } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "3way_8KB", buf)) { popts->memctl_interleaving_mode = FSL_DDR_3WAY_8KB_INTERLEAVING; #elif (CONFIG_NUM_DDR_CONTROLLERS == 4) } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "4way_1KB", buf)) { popts->memctl_interleaving_mode = FSL_DDR_4WAY_1KB_INTERLEAVING; } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "4way_4KB", buf)) { popts->memctl_interleaving_mode = FSL_DDR_4WAY_4KB_INTERLEAVING; } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "4way_8KB", buf)) { popts->memctl_interleaving_mode = FSL_DDR_4WAY_8KB_INTERLEAVING; #endif } else { popts->memctl_interleaving = 0; printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); } #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */ done: #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { /* test null first. if CONFIG_HWCONFIG is not defined, * hwconfig_subarg_cmp_f returns non-zero */ if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", "null", buf)) debug("bank interleaving disabled.\n"); else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", "cs0_cs1", buf)) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", "cs2_cs3", buf)) popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", "cs0_cs1_and_cs2_cs3", buf)) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", "cs0_cs1_cs2_cs3", buf)) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", "auto", buf)) popts->ba_intlv_ctl = auto_bank_intlv(pdimm); else printf("hwconfig has unrecognized parameter for bank_intlv.\n"); switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { case FSL_DDR_CS0_CS1_CS2_CS3: #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) if (pdimm[0].n_ranks < 4) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " "CS0+CS1+CS2+CS3 on controller %d, " "interleaving disabled!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE if (pdimm[0].n_ranks == 4) break; #endif if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " "CS0+CS1+CS2+CS3 on controller %d, " "interleaving disabled!\n", ctrl_num); } if (pdimm[0].capacity != pdimm[1].capacity) { popts->ba_intlv_ctl = 0; printf("Not identical DIMM size for " "CS0+CS1+CS2+CS3 on controller %d, " "interleaving disabled!\n", ctrl_num); } #endif break; case FSL_DDR_CS0_CS1: if (pdimm[0].n_ranks < 2) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " "CS0+CS1 on controller %d, " "interleaving disabled!\n", ctrl_num); } break; case FSL_DDR_CS2_CS3: #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) if (pdimm[0].n_ranks < 4) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for CS2+CS3 " "on controller %d, interleaving disabled!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) if (pdimm[1].n_ranks < 2) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for CS2+CS3 " "on controller %d, interleaving disabled!\n", ctrl_num); } #endif break; case FSL_DDR_CS0_CS1_AND_CS2_CS3: #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) if (pdimm[0].n_ranks < 4) { popts->ba_intlv_ctl = 0; printf("Not enough bank(CS) for CS0+CS1 and " "CS2+CS3 on controller %d, " "interleaving disabled!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) { popts->ba_intlv_ctl = 0; printf("Not enough bank(CS) for CS0+CS1 and " "CS2+CS3 on controller %d, " "interleaving disabled!\n", ctrl_num); } #endif break; default: popts->ba_intlv_ctl = 0; break; } } if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) { if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf)) popts->addr_hash = 0; else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "true", buf)) popts->addr_hash = 1; } if (pdimm[0].n_ranks == 4) popts->quad_rank_present = 1; ddr_freq = get_ddr_freq(ctrl_num) / 1000000; if (popts->registered_dimm_en) { popts->rcw_override = 1; popts->rcw_1 = 0x000a5a00; if (ddr_freq <= 800) popts->rcw_2 = 0x00000000; else if (ddr_freq <= 1066) popts->rcw_2 = 0x00100000; else if (ddr_freq <= 1333) popts->rcw_2 = 0x00200000; else popts->rcw_2 = 0x00300000; } fsl_ddr_board_options(popts, pdimm, ctrl_num); return 0; }
unsigned int fsl_ddr_get_mem_data_rate(void) { return get_ddr_freq(0); }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num > 1) { printf("Not supported controller number %d\n", ctrl_num); return; } if (!pdimm->n_ranks) return; if (popts->registered_dimm_en) pbsp = rdimms[0]; else pbsp = udimms[0]; /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found for %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; } else { panic("DIMM is not supported by this board"); } found: debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); popts->data_bus_width = 0; /* 64-bit data bus */ popts->bstopre = 0; /* enable auto precharge */ /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* * Rtt and Rtt_WR override */ popts->rtt_override = 0; /* Enable ZQ calibration */ popts->zq_en = 1; popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; /* optimize cpo for erratum A-009942 */ popts->cpo_sample = 0x61; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const board_specific_parameters_t *pbsp = &(board_specific_parameters[ctrl_num][0]); u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / sizeof(board_specific_parameters[0][0]); u32 i; ulong ddr_freq; /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If * there are two dimms in the controller, set odt_rd_cfg to 3 and * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i&1) { /* odd CS */ popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 1; } else { /* even CS */ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 1; } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { popts->cs_local_opts[i].odt_rd_cfg = 3; popts->cs_local_opts[i].odt_wr_cfg = 3; } } } /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; for (i = 0; i < num_params; i++) { if (ddr_freq >= pbsp->datarate_mhz_low && ddr_freq <= pbsp->datarate_mhz_high && pdimm->n_ranks == pbsp->n_ranks) { popts->cpo_override = 0xff; /* force auto CPO calibration */ popts->write_data_delay = 2; popts->clk_adjust = 5; /* Force value to be 5/8 clock cycle */ popts->twoT_en = pbsp->force_2T; } pbsp++; } /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xa; popts->wrlvl_start = 0x7; /* * Rtt and Rtt_WR override */ popts->rtt_override = 1; popts->rtt_override_value = DDR3_RTT_120_OHM; popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ /* Enable ZQ calibration */ popts->zq_en = 1; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const board_specific_parameters_t *pbsp; u32 num_params; u32 i; ulong ddr_freq; int matched = 0; if (!pdimm->n_ranks) return; if (popts->registered_dimm_en) { pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]); num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) / sizeof(board_specific_parameters_rdimm[0][0]); } else { pbsp = &(board_specific_parameters_udimm[ctrl_num][0]); num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) / sizeof(board_specific_parameters_udimm[0][0]); } /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If * there are two dimms in the controller, set odt_rd_cfg to 3 and * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i&1) { /* odd CS */ popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 0; } else { /* even CS */ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 4; } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { popts->cs_local_opts[i].odt_rd_cfg = 3; popts->cs_local_opts[i].odt_wr_cfg = 3; } } } /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; for (i = 0; i < num_params; i++) { if (ddr_freq >= pbsp->datarate_mhz_low && ddr_freq <= pbsp->datarate_mhz_high && pdimm->n_ranks == pbsp->n_ranks) { popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twoT_en = pbsp->force_2T; matched = 1; break; } pbsp++; } if (!matched) printf("Warning: board specific timing not found!\n"); /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num > 1) { printf("Not supported controller number %d\n", ctrl_num); return; } if (!pdimm->n_ranks) return; /* * we use identical timing for all slots. If needed, change the code * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; */ pbsp = udimms[0]; /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found for %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; } else { panic("DIMM is not supported by this board"); } found: debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); popts->half_strength_driver_enable = 0; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* Enable ZQ calibration */ popts->zq_en = 1; /* Enable DDR hashing */ popts->addr_hash = 1; popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) fsl_ddr_setup_0v9_volt(popts); #endif popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num) { printf("Wrong parameter for controller number %d", ctrl_num); return; } if (!pdimm->n_ranks) return; pbsp = dimm0; /* * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found " "for data rate %lu MT/s!\n" "Trying to use the highest speed (%u) parameters\n", ddr_freq, pbsp_highest->datarate_mhz_high); popts->cpo_override = pbsp_highest->cpo; popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } found: /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; /* Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* Rtt and Rtt_WR override */ popts->rtt_override = 0; /* Enable ZQ calibration */ popts->zq_en = 1; /* DHC_EN =1, ODT = 60 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_params *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num) { printf("Wrong parameter for controller number %d", ctrl_num); return; } if (!pdimm->n_ranks) return; if (popts->registered_dimm_en) pbsp = rdimm; else pbsp = udimm; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->twoT_en = pbsp->force_2T; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found " "for data rate %lu MT/s!\n" "Trying to use the highest speed (%u) parameters\n", ddr_freq, pbsp_highest->datarate_mhz_high); popts->cpo_override = pbsp_highest->cpo; popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->twoT_en = pbsp_highest->force_2T; } else { panic("DIMM is not supported by this board"); } found: /* * The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered. * However SPD still claims CL=7 is supported. Extensive tests * confirmed this board cannot work stably with CL=7 with this * particular DIMM. */ if (ddr_freq >= 800 && ddr_freq < 1066 && \ !strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) { popts->cas_latency_override = 1; popts->cas_latency_override_value = 8; debug("Override CL to 8\n"); } /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* * Rtt and Rtt_WR override */ popts->rtt_override = 0; /* Enable ZQ calibration */ popts->zq_en = 1; /* DHC_EN =1, ODT = 60 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const board_specific_parameters_t *pbsp = &(board_specific_parameters[ctrl_num][0]); u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / sizeof(board_specific_parameters[0][0]); u32 i; u32 j; ulong ddr_freq; /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If * there are two dimms in the controller, set odt_rd_cfg to 3 and * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i&1) { /* odd CS */ popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 0; } else { /* even CS */ if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) && (pdimm[i/2].n_ranks != 0)) { popts->cs_local_opts[i].odt_rd_cfg = 3; popts->cs_local_opts[i].odt_wr_cfg = 3; } else { popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 4; } } } /* Get clk_adjust, cpo, write_data_delay, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { if (pdimm[j].n_ranks > 0) { for (i = 0; i < num_params; i++) { if (ddr_freq >= pbsp->datarate_mhz_low && ddr_freq <= pbsp->datarate_mhz_high && pdimm[j].n_ranks == pbsp->n_ranks) { popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; break; } pbsp++; } } } if (i == num_params) { printf("Warning: board specific timing not found " "for data rate %lu MT/s!\n", ddr_freq); } /* 2T timing enable */ popts->twoT_en = 1; }
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num > 3) { printf("Not supported controller number %d\n", ctrl_num); return; } if (!pdimm->n_ranks) return; pbsp = udimms[0]; /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; popts->cpo_override = pbsp->cpo_override; popts->write_data_delay = pbsp->write_data_delay; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found for %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; } else { panic("DIMM is not supported by this board"); } found: debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; popts->otf_burst_chop_en = 0; popts->burst_length = DDR_BL8; /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 1; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* * Rtt and Rtt_WR override */ popts->rtt_override = 0; /* Enable ZQ calibration */ popts->zq_en = 1; #ifdef CONFIG_SYS_FSL_DDR4 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ #else popts->cswl_override = DDR_CSWL_CS0; /* optimize cpo for erratum A-009942 */ popts->cpo_sample = 0x58; /* DHC_EN =1, ODT = 75 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); #endif }