int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
size_t size;
SI val;
check_desc (sd);
if (!check_regno (regno))
return -1;
size = reg_size (regno);
if (length != size)
return -1;
val = get_le (buf, length);
if (regno == sim_rl78_pc_regnum)
{
pc = val;
/* The rl78 program counter is 20 bits wide. Ensure that GDB
hasn't picked up any stray bits. This has occurred when performing
a GDB "return" command in which the return address is obtained
from a 32-bit container on the stack. */
assert ((pc & ~0x0fffff) == 0);
}
else
memory[reg_addr (regno)] = val;
return size;
}
int main(int argc, char *argv[]) {
int rawfd; int recno = 0;
unsigned int pid = 0;
struct stat fstat;
if(argc < 2) {
fprintf(stderr,"usage: expand <logfn> [pid]\n");
exit(1);
}
if( (rawfd=open(argv[1], O_RDONLY)) < 0 ) {
fprintf(stderr,"couldn't connect to raw log: %s\n", argv[1]);
fflush(stderr); exit(1);
}
if(argc == 3) {
pid = atoi(argv[2]);
}
if( stat(argv[1], &fstat) < 0 ) {
perror("stat");
exit(1);
}
while (1) {
logentry_thaw_t *le = get_le(rawfd,0); // 0 = non-persistant
if(le == NULL) break;
//check_le(le);
recno++;
if(BUF_DEBUG) { fprintf(stdout, "r%6d: \n",recno); fflush(stderr); }
if(pid && le->fz.pid != pid) {
// no output
} else {
output_le(stdout,le);
}
free_le(le);
}
fprintf(stdout, "total: %d\n",recno);
fprintf(stdout, "bytes: %d\n",bytes_seen);
if(fstat.st_size != bytes_seen) {
fprintf(stdout, "ERROR! size mismatch (fstat=%ld,used=%ld)\n",
(long)fstat.st_size,(long)bytes_seen);
exit(1);
}
return 1;
}
int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
size_t size;
SI val;
check_desc (sd);
if (!check_regno (regno))
return -1;
size = reg_size (regno);
if (length != size)
return -1;
val = get_le (buf, length);
if (regno == sim_rl78_pc_regnum)
pc = val;
else
memory[reg_addr (regno)] = val;
return size;
}
int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
size_t size;
check_desc (sd);
if (!check_regno (regno))
return -1;
size = reg_size (regno);
if (length == size)
{
DI val = get_le (buf, length);
switch (regno)
{
case m32c_sim_reg_r0_bank0:
regs.r[0].r_r0 = val & 0xffff;
break;
case m32c_sim_reg_r1_bank0:
regs.r[0].r_r1 = val & 0xffff;
break;
case m32c_sim_reg_r2_bank0:
regs.r[0].r_r2 = val & 0xffff;
break;
case m32c_sim_reg_r3_bank0:
regs.r[0].r_r3 = val & 0xffff;
break;
case m32c_sim_reg_a0_bank0:
regs.r[0].r_a0 = val & addr_mask;
break;
case m32c_sim_reg_a1_bank0:
regs.r[0].r_a1 = val & addr_mask;
break;
case m32c_sim_reg_fb_bank0:
regs.r[0].r_fb = val & addr_mask;
break;
case m32c_sim_reg_sb_bank0:
regs.r[0].r_sb = val & addr_mask;
break;
case m32c_sim_reg_r0_bank1:
regs.r[1].r_r0 = val & 0xffff;
break;
case m32c_sim_reg_r1_bank1:
regs.r[1].r_r1 = val & 0xffff;
break;
case m32c_sim_reg_r2_bank1:
regs.r[1].r_r2 = val & 0xffff;
break;
case m32c_sim_reg_r3_bank1:
regs.r[1].r_r3 = val & 0xffff;
break;
case m32c_sim_reg_a0_bank1:
regs.r[1].r_a0 = val & addr_mask;
break;
case m32c_sim_reg_a1_bank1:
regs.r[1].r_a1 = val & addr_mask;
break;
case m32c_sim_reg_fb_bank1:
regs.r[1].r_fb = val & addr_mask;
break;
case m32c_sim_reg_sb_bank1:
regs.r[1].r_sb = val & addr_mask;
break;
case m32c_sim_reg_usp:
regs.r_usp = val & addr_mask;
break;
case m32c_sim_reg_isp:
regs.r_isp = val & addr_mask;
break;
case m32c_sim_reg_pc:
regs.r_pc = val & membus_mask;
break;
case m32c_sim_reg_intb:
regs.r_intbl = (val & membus_mask) & 0xffff;
regs.r_intbh = (val & membus_mask) >> 16;
break;
case m32c_sim_reg_flg:
regs.r_flags = val & 0xffff;
break;
/* These registers aren't implemented by the minisim. */
case m32c_sim_reg_svf:
case m32c_sim_reg_svp:
case m32c_sim_reg_vct:
case m32c_sim_reg_dmd0:
case m32c_sim_reg_dmd1:
case m32c_sim_reg_dct0:
case m32c_sim_reg_dct1:
case m32c_sim_reg_drc0:
case m32c_sim_reg_drc1:
case m32c_sim_reg_dma0:
case m32c_sim_reg_dma1:
case m32c_sim_reg_dsa0:
case m32c_sim_reg_dsa1:
case m32c_sim_reg_dra0:
case m32c_sim_reg_dra1:
return 0;
default:
fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
regno);
return 0;
}
}
int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
{
size_t size;
DI val;
check_desc (sd);
if (!check_regno (regno))
return 0;
size = reg_size (regno);
if (length != size)
return 0;
if (rx_big_endian)
val = get_be (buf, length);
else
val = get_le (buf, length);
switch (regno)
{
case sim_rx_r0_regnum:
put_reg (0, val);
break;
case sim_rx_r1_regnum:
put_reg (1, val);
break;
case sim_rx_r2_regnum:
put_reg (2, val);
break;
case sim_rx_r3_regnum:
put_reg (3, val);
break;
case sim_rx_r4_regnum:
put_reg (4, val);
break;
case sim_rx_r5_regnum:
put_reg (5, val);
break;
case sim_rx_r6_regnum:
put_reg (6, val);
break;
case sim_rx_r7_regnum:
put_reg (7, val);
break;
case sim_rx_r8_regnum:
put_reg (8, val);
break;
case sim_rx_r9_regnum:
put_reg (9, val);
break;
case sim_rx_r10_regnum:
put_reg (10, val);
break;
case sim_rx_r11_regnum:
put_reg (11, val);
break;
case sim_rx_r12_regnum:
put_reg (12, val);
break;
case sim_rx_r13_regnum:
put_reg (13, val);
break;
case sim_rx_r14_regnum:
put_reg (14, val);
break;
case sim_rx_r15_regnum:
put_reg (15, val);
break;
case sim_rx_isp_regnum:
put_reg (isp, val);
break;
case sim_rx_usp_regnum:
put_reg (usp, val);
break;
case sim_rx_intb_regnum:
put_reg (intb, val);
break;
case sim_rx_pc_regnum:
put_reg (pc, val);
break;
case sim_rx_ps_regnum:
put_reg (psw, val);
break;
case sim_rx_bpc_regnum:
put_reg (bpc, val);
break;
case sim_rx_bpsw_regnum:
put_reg (bpsw, val);
break;
case sim_rx_fintv_regnum:
put_reg (fintv, val);
break;
case sim_rx_fpsw_regnum:
put_reg (fpsw, val);
break;
default:
fprintf (stderr, "rx minisim: unrecognized register number: %d\n",
regno);
return -1;
}
return size;
}
inline T get_le(const Ch*& s) { T n; get_le(s, n); return n; }
inline uint64_t get64le(const Ch*& s) { uint64_t n; get_le(s, n); return n; }
inline uint32_t get32le(const Ch*& s) { uint32_t n; get_le(s, n); return n; }
inline uint16_t get16le(const Ch*& s) { uint16_t n; get_le(s, n); return n; }
