struct status_data dev_status_handle()
{
struct status_data dev_status;
dev_status.cpu_usage = get_cpuoccupy_status();
dev_status.ibeacon_status = get_ibeacon_status();
dev_status.wifi_collect_module = get_wifi_module_status();
dev_status.net_type = get_net_type();
dev_status.mem_usage = get_memoccupy_status();
uagent_printf(MSG_ERROR,"The cpu occupy rate is %d, the ibeacon status"
"is %d, the wifi collect module status is %d, the net type is %d,"
"the mem occupy is %d.\n",
dev_status.cpu_usage, dev_status.ibeacon_status, dev_status.wifi_collect_module,
dev_status.net_type,dev_status.mem_usage);
return dev_status;
}
void dru_init(void)
{
unsigned int i=0,data;
unsigned char gain_test,en_test,lo;
unsigned short temp_test,epld_test;
power_sw_init();
power_sw_open();
#ifdef CONFIG_KSZ8873
dru_ksz8873_init();
printf("configure ksz8873\n");
#endif
#ifdef CONFIG_AD9523
if(get_device_type()==DEVICE_TYPE_MAIN){
dru_ad9523_init_m();
}else{
dru_ad9523_init_s();
}
//dru_ad9523_init();
spi_delay(SPI_CONFIG_DELAY);
printf("configure ad9523\n");
#endif
#ifdef DOWNLOAD_FPGA
if(get_device_type()==DEVICE_TYPE_MAIN){
dru_fpga_download(FPGA_FILE_LENGTH,"/ramDisk/fpga_main.rbf");//1357101
}else if(get_device_type()==DEVICE_TYPE_RAU){
dru_fpga_download(FPGA_FILE_LENGTH,"/ramDisk/fpga_rrs.rbf");//1357101
}else if(get_device_type()==DEVICE_TYPE_EXPEND){
dru_fpga_download(FPGA_FILE_LENGTH,"/ramDisk/fpga_exp.rbf");//1357101
}
printf("configure fpga\n");
#endif
/*#ifdef CONFIG_LMX2531
if(get_net_group() == 0x331){ // µçÐÅÈýÍø
// dru_lmx2531_cdma_init_m();
dru_lmx2531_fdd_lte1_config(1711400);
dru_lmx2531_fdd_lte2_config(1711400);
}else{
if(get_device_type()==DEVICE_TYPE_MAIN){
//dru_lmx2531_wcdma_config(1925340);// main
dru_lmx2531_config(1879260,3,0,LQ1910E_6144M);
}else{
dru_lmx2531_wcdma_config(1925340); //RAU
}//
if(get_net_type() == 1){ // 1:gsm 2:dcs
dru_lmx2531_config(805760,1,1,LQ1650E_6144M);
//dru_lmx2531_gsm_init_m();
}else{
dru_lmx2531_dcs_init();
}
if(get_device_type()==DEVICE_TYPE_MAIN){
dru_lmx2531_config(2206760,2,0,LQ2265E_6144M);
dru_lmx2531_config(2206760,4,0,LQ2265E_6144M);
//dru_lmx2531_lte1_config(2252840);// main
//dru_lmx2531_lte2_config(2252840);// main
}else{
dru_lmx2531_lte1_config(2252840); // RAU
dru_lmx2531_lte2_config(2252840);
}
}*/
if(get_net_group() == 0x331){ // µçÐÅÈýÍø
// dru_lmx2531_cdma_init_m();
dru_lmx2531_fdd_lte1_config(1711400);
dru_lmx2531_fdd_lte2_config(1711400);
}else{
if(get_device_type()==DEVICE_TYPE_MAIN){
//dru_lmx2531_wcdma_config(1925340);// main
if(dru_dev_p->dev_vco<0X20){
dru_lmx2531_config(1879260,3,0,LQ1910E_6144M);
}else if((dru_dev_p->dev_vco>0X20)&&(dru_dev_p->dev_vco<0x30)){
dru_lmx2581_config(187926,3);
}
}
if(get_net_type() == 1){ // 1:gsm 2:dcs
//dru_lmx2531_config(805760,1,1,LQ1650E_6144M);
if(dru_dev_p->dev_vco<0X20){
dru_lmx2531_config(805760,1,1,LQ1650E_6144M);
}else if(dru_dev_p->dev_vco>0X20&&dru_dev_p->dev_vco<0x30){
dru_lmx2581_config(80576,1);
}
//dru_lmx2531_gsm_init_m();
}else{
dru_lmx2531_dcs_init();
}
if(get_device_type()==DEVICE_TYPE_MAIN){
//dru_lmx2531_config(2206760,2,0,LQ2265E_6144M);
//dru_lmx2531_config(2206760,4,0,LQ2265E_6144M);
if(dru_dev_p->dev_vco==DEV_LM2531_CMGSM_LTEE){
//dru_lmx2531_config(805760,1,1,LQ1650E_6144M);
dru_lmx2531_config(2206760,2,0,LQ2265E_6144M);
dru_lmx2531_config(2206760,4,0,LQ2265E_6144M);
}else if(dru_dev_p->dev_vco==DEV_LM2581_CMGSM_LTEE){
dru_lmx2581_config(220676,2);
dru_lmx2581_config(220676,4);
}
if(dru_dev_p->dev_vco==DEV_LM2531_CMGSM_LTED){
//dru_lmx2531_config(805760,1,1,LQ1650E_6144M);
dru_lmx2531_config(2466760,2,0,LQ2570E_6144M);
dru_lmx2531_config(2466760,4,0,LQ2570E_6144M);
}else if(dru_dev_p->dev_vco==DEV_LM2581_CMGSM_LTED){
dru_lmx2581_config(246676,2);
dru_lmx2581_config(246676,4);
}
//dru_lmx2531_lte1_config(2252840);// main
//dru_lmx2531_lte2_config(2252840);// main
}
}
printf("%x\n",epld_test);
emif_epld_spi_channel(10);
emif_epld_spi_channel(10);
emif_fpga_ddc_carrier_f8_write(0,25);
emif_fpga_ddc_carrier_f8_write(1,50);
emif_fpga_ddc_carrier_f8_write(2,75);
emif_fpga_ddc_carrier_f8_write(3,100);
emif_fpga_ddc_carrier_f8_write(4,125);
emif_fpga_ddc_carrier_f8_write(5,150);
emif_fpga_ddc_carrier_f8_write(6,175);
emif_fpga_ddc_carrier_f8_write(7,200);
emif_fpga_ddc_carrier_m8_write(0,768-200);
emif_fpga_ddc_carrier_m8_write(1,768-175);
emif_fpga_ddc_carrier_m8_write(2,768-150);
emif_fpga_ddc_carrier_m8_write(3,768-125);
emif_fpga_ddc_carrier_m8_write(4,768-100);
emif_fpga_ddc_carrier_m8_write(5,768-75);
emif_fpga_ddc_carrier_m8_write(6,768-50);
emif_fpga_ddc_carrier_m8_write(7,768-25);
//
emif_fpga_duc_carrier_f8_write(0,25);
emif_fpga_duc_carrier_f8_write(1,50);
emif_fpga_duc_carrier_f8_write(2,75);
emif_fpga_duc_carrier_f8_write(3,100);
emif_fpga_duc_carrier_f8_write(4,125);
emif_fpga_duc_carrier_f8_write(5,150);
emif_fpga_duc_carrier_f8_write(6,175);
emif_fpga_duc_carrier_f8_write(7,200);
emif_fpga_duc_carrier_m8_write(0,768-200);
emif_fpga_duc_carrier_m8_write(1,768-175);
emif_fpga_duc_carrier_m8_write(2,768-150);
emif_fpga_duc_carrier_m8_write(3,768-125);
emif_fpga_duc_carrier_m8_write(4,768-100);
emif_fpga_duc_carrier_m8_write(5,768-75);
emif_fpga_duc_carrier_m8_write(6,768-50);
emif_fpga_duc_carrier_m8_write(7,768-25);
//*DRU_REGADDR(fpga_base_addr, ADC_SOURCE_SEL)= 1;//enable internal dds for adc_source
//*DRU_REGADDR(fpga_base_addr, LOOP_BACK_SEL)= 1; //enable loop_back_sel
*DRU_REGADDR(fpga_base_addr, MASK_CARRIER)= 0xfffe;
*DRU_REGADDR(fpga_base_addr, DUC_RST)= 0;
*DRU_REGADDR(fpga_base_addr, DUC_RST)= 1; // disable duc rst
spi_delay(10000);
*DRU_REGADDR(fpga_base_addr, DUC_RST)= 0;
*DRU_REGADDR(fpga_base_addr, LTE1_ATT)= 13;
*DRU_REGADDR(fpga_base_addr, LTE2_ATT)= 13;
*DRU_REGADDR(fpga_base_addr, WCDMA_ATT)= 13;
*DRU_REGADDR(fpga_base_addr, GSM_ATT)= 13;
*DRU_REGADDR(fpga_base_addr, CPU_AGC_EN)= 0;
*DRU_REGADDR(fpga_base_addr, CPU_AGC_EN)= 1;
spi_delay(1000);
*DRU_REGADDR(fpga_base_addr, CPU_AGC_EN)= 0;
//#endif
#ifdef CONFIG_ADS58C48
dru_ads58c48_init();
if(dru_dev_p->dev_vco<0X20){
dru_ads58c48_init();
}else{
dru_ads58c48_init_2581();
}
printf("configure ads58c48\n");
#endif
dru_dac3484_init();
*DRU_REGADDR(fpga_base_addr, DAC_SYNC)=0;
*DRU_REGADDR(fpga_base_addr, DAC_SYNC)=1;
printf("configure dac3484\n");
*DRU_REGADDR(fpga_base_addr, LOOP_BACK_SEL)=1;
*DRU_REGADDR(fpga_base_addr, AGC_STEP)=1;
//dac3484_td_qmc_phase_cd(10);
*DRU_REGADDR(fpga_base_addr, DAC_SYNC)=0;
*DRU_REGADDR(fpga_base_addr, DAC_SYNC)=1;
*DRU_REGADDR(fpga_base_addr, LTE1_GAIN)=8192;
*DRU_REGADDR(fpga_base_addr, LTE2_GAIN)= 8192;
*DRU_REGADDR(fpga_base_addr, TD_GAIN)= 8192;
*DRU_REGADDR(fpga_base_addr, GSM_GAIN)= 8192;
*DRU_REGADDR(fpga_base_addr, ADC_SOURCE_FREQENCY)= 192+10;
*DRU_REGADDR(fpga_base_addr, ADC_SOURCE_SEL)= 0;
*DRU_REGADDR(fpga_base_addr, LOOP_BACK_SEL)= 1; //enable loop_back_sel
lo=*DRU_REGADDR(epld_base_addr, 0x12);
if((lo&(1<<0))!=0)
printf("±¾Õñ1Ëø¶¨\n");
else
printf("±¾Õñ1ʧËø\n");
if((lo&(1<<1))!=0)
printf("±¾Õñ2Ëø¶¨\n");
else
printf("±¾Õñ2ʧËø\n");
if((lo&(1<<2))!=0)
printf("±¾Õñ3Ëø¶¨\n");
else
printf("±¾Õñ3ʧËø\n");
if((lo&(1<<3))!=0)
printf("±¾Õñ4Ëø¶¨\n");
else
printf("±¾Õñ4ʧËø\n");
}
