void main(void) { timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); timestamp_add_now(TS_BEFORE_INITRAM); sdram_init(get_sdram_config()); timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); timestamp_add_now(TS_END_ROMSTAGE); run_ramstage(); }
static void tegra210_init(void *chip_info) { struct tegra_revision rev; tegra_revision_info(&rev); printk(BIOS_INFO, "chip %x rev %02x.%x\n", rev.chip_id, rev.major, rev.minor); /* Save sdram parameters to scratch regs to be used in LP0 resume */ sdram_lp0_save_params(get_sdram_config()); printk(BIOS_INFO, "sdram params saved.\n"); }
static void __attribute__((noinline)) romstage(void) { timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); console_init(); exception_init(); sdram_init(get_sdram_config()); /* used for MMU and CBMEM setup, in MB */ u32 dram_start_mb = (uintptr_t)_dram/MiB; u32 dram_end_mb = sdram_max_addressable_mb(); u32 dram_size_mb = dram_end_mb - dram_start_mb; configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), DCACHE_WRITEBACK); /* DRAM is cached. */ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); /* The space above DRAM is uncached. */ if (dram_end_mb < 4096) mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); mmu_disable_range(0, 1); dcache_mmu_enable(); /* * A watchdog reset only resets part of the system so it ends up in * a funny state. If that happens, we need to reset the whole machine. */ if (power_reset_status() == POWER_RESET_WATCHDOG) { printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n"); hard_reset(); } /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); early_mainboard_init(); run_ramstage(); }
void main(void) { #if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); #endif console_init(); configure_l2ctlr(); tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time); timestamp_add(TS_BEFORE_INITRAM, before_dram_time); timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif #if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) void *entry = vboot2_load_ramstage(); if (entry != NULL) stage_exit(entry); #endif run_ramstage(); }
void platform_romstage_main(void) { tsadc_init(TSHUT_POL_HIGH); /* Init DVS to conservative values. */ init_dvs_outputs(); prepare_sdmmc(); prepare_usb(); sdram_init(get_sdram_config()); mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB, CACHED_MEM); mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent), UNCACHED_MEM); }
void romstage(void) { timestamp_add_now(TS_START_ROMSTAGE); console_init(); exception_init(); printk(BIOS_INFO, "T132: romstage here\n"); #if CONFIG_BOOTROM_SDRAM_INIT printk(BIOS_INFO, "T132 romstage: SDRAM init done by BootROM, RAMCODE = %d\n", sdram_get_ram_code()); #else sdram_init(get_sdram_config()); printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); #endif timestamp_add_now(TS_AFTER_INITRAM); /* * Trust Zone needs to be initialized after the DRAM initialization * because carveout registers are programmed during DRAM init. * cbmem_initialize() is dependent on the Trust Zone region * initalization because CBMEM lives right below the Trust Zone which * needs to be properly identified. */ trustzone_region_init(); /* * When romstage is running it's always on the reboot path -- never a * resume path where cbmem recovery is required. Therefore, always * initialize the cbmem area to be empty. */ cbmem_initialize_empty(); ccplex_cpu_prepare(); printk(BIOS_INFO, "T132 romstage: cpu prepare done\n"); ccplex_load_mts(); printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); romstage_mainboard_init(); run_ramstage(); }
void main(void) { console_init(); tsadc_init(TSHUT_POL_HIGH); exception_init(); /* Init DVS to conservative values. */ init_dvs_outputs(); prepare_usb(); sdram_init(get_sdram_config()); mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM); mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); cbmem_initialize_empty(); run_ramstage(); }