u32 omap4_ddr_clk(void) { u32 ddr_clk, sys_clk_khz; const struct dpll_params *core_dpll_params; sys_clk_khz = get_sys_clk_freq() / 1000; core_dpll_params = get_core_dpll_params(); debug("sys_clk %d\n ", sys_clk_khz * 1000); /* Find Core DPLL locked frequency first */ ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / (core_dpll_params->n + 1); /* * DDR frequency is PHY_ROOT_CLK/2 * PHY_ROOT_CLK = Fdpll/2/M2 */ ddr_clk = ddr_clk / 4 / core_dpll_params->m2; ddr_clk *= 1000; /* convert to Hz */ debug("ddr_clk %d\n ", ddr_clk); return ddr_clk; }
static void setup_usb_dpll(void) { const struct dpll_params *params; u32 sys_clk_khz, sd_div, num, den; sys_clk_khz = get_sys_clk_freq() / 1000; /* * USB: * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) * - where CLKINP is sys_clk in MHz * Use CLKINP in KHz and adjust the denominator accordingly so * that we have enough accuracy and at the same time no overflow */ params = get_usb_dpll_params(*dplls_data); num = params->m * sys_clk_khz; den = (params->n + 1) * 250 * 1000; num += den - 1; sd_div = num / den; clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); /* Now setup the dpll with the regular function */ do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); }
/** * omap_vc_init() - Initialization for Voltage controller * @speed_khz: I2C buspeed in KHz */ void omap_vc_init(u16 speed_khz) { u32 val; u32 sys_clk_khz, cycles_hi, cycles_low; sys_clk_khz = get_sys_clk_freq() / 1000; if (speed_khz > 400) { puts("higher speed requested - throttle to 400Khz\n"); speed_khz = 400; } /* * Setup the dedicated I2C controller for Voltage Control * I2C clk - high period 40% low period 60% */ speed_khz /= 10; cycles_hi = sys_clk_khz * 4 / speed_khz; cycles_low = sys_clk_khz * 6 / speed_khz; /* values to be set in register - less by 5 & 7 respectively */ cycles_hi -= 5; cycles_low -= 7; val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); writel(val, (*prcm)->prm_vc_cfg_i2c_clk); val = CONFIG_OMAP_VC_I2C_HS_MCODE << PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT; /* No HS mode for now */ val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT; writel(val, (*prcm)->prm_vc_cfg_i2c_mode); }
static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs) { u32 rate = get_sys_clk_freq()/1000000; u32 val; val = readl((*ctrl)->control_phy_power_usb); val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK); val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON); val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT; writel(val, (*ctrl)->control_phy_power_usb); }
static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 *pipe3) { u32 rate; struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; rate = get_sys_clk_freq(); for (; dpll_map->rate; dpll_map++) { if (rate == dpll_map->rate) return &dpll_map->params; } printf("%s: No DPLL configuration for %u Hz SYS CLK\n", __func__, rate); return NULL; }
u32 omap_ddr_clk(void) { u32 ddr_clk, sys_clk_khz, omap_rev, divider; const struct dpll_params *core_dpll_params; omap_rev = omap_revision(); sys_clk_khz = get_sys_clk_freq() / 1000; core_dpll_params = get_core_dpll_params(*dplls_data); debug("sys_clk %d\n ", sys_clk_khz * 1000); /* Find Core DPLL locked frequency first */ ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / (core_dpll_params->n + 1); if (omap_rev < OMAP5430_ES1_0) { /* * DDR frequency is PHY_ROOT_CLK/2 * PHY_ROOT_CLK = Fdpll/2/M2 */ divider = 4; } else { /* * DDR frequency is PHY_ROOT_CLK * PHY_ROOT_CLK = Fdpll/2/M2 */ divider = 2; } ddr_clk = ddr_clk / divider / core_dpll_params->m2; ddr_clk *= 1000; /* convert to Hz */ debug("ddr_clk %d\n ", ddr_clk); return ddr_clk; }
static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on) { u32 val, rate; val = readl(pipe3->power_reg); rate = get_sys_clk_freq(); rate = rate/1000000; if (on) { val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; val |= rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; } else { val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; } writel(val, pipe3->power_reg); }
/* * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva * We set the maximum voltages allowed here because Smart-Reflex is not * enabled in bootloader. Voltage initialization in the kernel will set * these to the nominal values after enabling Smart-Reflex */ static void scale_vcores(void) { u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev; sys_clk_khz = get_sys_clk_freq() / 1000; /* * Setup the dedicated I2C controller for Voltage Control * I2C clk - high period 40% low period 60% */ cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; /* values to be set in register - less by 5 & 7 respectively */ cycles_hi -= 5; cycles_low -= 7; temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); writel(temp, &prcm->prm_vc_cfg_i2c_clk); /* Disable high speed mode and all advanced features */ writel(0x0, &prcm->prm_vc_cfg_i2c_mode); omap4_rev = omap_revision(); /* TPS - supplies vdd_mpu on 4460 */ if (omap4_rev >= OMAP4460_ES1_0) { volt = 1430; do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt); } /* * VCORE 1 * * 4430 : supplies vdd_mpu * Setting a high voltage for Nitro mode as smart reflex is not enabled. * We use the maximum possible value in the AVS range because the next * higher voltage in the discrete range (code >= 0b111010) is way too * high * * 4460 : supplies vdd_core */ if (omap4_rev < OMAP4460_ES1_0) { volt = 1417; do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); } else { volt = 1200; do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); } /* VCORE 2 - supplies vdd_iva */ volt = 1200; do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); /* * VCORE 3 * 4430 : supplies vdd_core * 4460 : not connected */ if (omap4_rev < OMAP4460_ES1_0) { volt = 1200; do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); } }
static void setup_non_essential_dplls(void) { u32 sys_clk_khz, abe_ref_clk; u32 sysclk_ind, sd_div, num, den; const struct dpll_params *params; sysclk_ind = get_sys_clk_index(); sys_clk_khz = get_sys_clk_freq() / 1000; /* IVA */ clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); do_setup_dpll(&prcm->cm_clkmode_dpll_iva, &iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK); /* * USB: * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) * - where CLKINP is sys_clk in MHz * Use CLKINP in KHz and adjust the denominator accordingly so * that we have enough accuracy and at the same time no overflow */ params = &usb_dpll_params_1920mhz[sysclk_ind]; num = params->m * sys_clk_khz; den = (params->n + 1) * 250 * 1000; num += den - 1; sd_div = num / den; clrsetbits_le32(&prcm->cm_clksel_dpll_usb, CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); /* Now setup the dpll with the regular function */ do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK); #ifdef CONFIG_SYS_OMAP4_ABE_SYSCK params = &abe_dpll_params_sysclk_196608khz[sysclk_ind]; abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; #else params = &abe_dpll_params_32k_196608khz; abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; /* * We need to enable some additional options to achieve * 196.608MHz from 32768 Hz */ setbits_le32(&prcm->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| CM_CLKMODE_DPLL_LPMODE_EN_MASK| CM_CLKMODE_DPLL_REGM4XEN_MASK); /* Spend 4 REFCLK cycles at each stage */ clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_RAMP_RATE_MASK, 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); #endif /* Select the right reference clk */ clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); /* Lock the dpll */ do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK); }