/* Initialise xenbus. */
void init_xenbus(void)
{
portBASE_TYPE ret;
DEBUG("init_xenbus called.\n");
init_waitqueue_head(&xb_waitq);
init_waitqueue_head(&req_wq);
init_waitqueue_head(&xenbus_watch_queue);
watches = NULL;
xb_write_sem = xSemaphoreCreateMutex();
arch_init_xenbus(&xenstore_buf, &store_evtchn);
DEBUG("init_xenbus: buf = 0x%x, evtchn = %d\n", xenstore_buf, store_evtchn);
ret = xTaskCreate(xenbus_thread_func, ( signed portCHAR * ) "xenbusTask", 4096,
NULL, configXENBUS_TASK_PRIORITY, NULL);
if (ret != pdPASS) {
printk("Error creating xenbus task, status was %d\n", ret);
BUG();
}
bind_evtchn(store_evtchn, xenbus_evtchn_handler, NULL);
unmask_evtchn(store_evtchn);
gic_register_handler(EVENT_IRQ, handle_event);
gic_enable_interrupt(EVENT_IRQ /* interrupt number */,
0x1 /*cpu_set*/, 1 /*level_sensitive*/, 0 /* ppi */);
gic_set_priority(EVENT_IRQ, configEVENT_IRQ_PRIORITY << portPRIORITY_SHIFT);
printk("Xen event IRQ enabled at priority %d\n", configEVENT_IRQ_PRIORITY);
printk("xenbus initialised on event channel %d\n", store_evtchn);
}
void vConfigureTickInterrupt( void )
{
setup_timer();
gic_register_handler(VIRTUAL_TIMER_IRQ, handle_timer_interrupt);
gic_enable_interrupt(VIRTUAL_TIMER_IRQ /* interrupt number */,
0x1 /*cpu_set*/, 1 /*level_sensitive*/, 1 /* ppi */);
gic_set_priority(VIRTUAL_TIMER_IRQ, configTICK_PRIORITY << portPRIORITY_SHIFT);
printk("Timer event IRQ enabled at priority %d\n", configTICK_PRIORITY);
}
void
timers_init(int timeslice) {
/* The timeslice is in ms, so divide by 1000. */
timeslice_ticks= timeslice * a15_gt_frequency() / 1000;
MSG("System counter frequency is %uHz.\n", a15_gt_frequency());
MSG("Timeslice interrupt every %u ticks (%dms).\n",
timeslice_ticks, timeslice);
a15_gt_init();
/* Enable the interrupt. */
gic_enable_interrupt(LOCAL_TIMER_IRQ, 0, 0, 0, 0);
/* Set the first timeout. */
a15_gt_timeout(timeslice_ticks);
/* We use the system counter for timestamps, which doesn't need any
* further initialisation. */
}
static void pit_config(uint32_t timeslice, uint8_t pit_id)
{
sp804_pit_t *pit;
if(pit_id == PIT0_ID)
pit = &pit0;
else if(pit_id == PIT1_ID)
pit = &pit1;
else
panic("Unsupported PIT ID: %"PRIu32, pit_id);
// PIT timer
uint32_t load1 = timeslice * tsc_hz / 1000;
uint32_t load2 = timeslice * tsc_hz / 1000;
sp804_pit_Timer1Load_wr(pit, load1);
sp804_pit_Timer2Load_wr(pit, load2);
//configure timer 1
sp804_pit_Timer1Control_one_shot_wrf(pit, 0);
sp804_pit_Timer1Control_timer_size_wrf(pit, sp804_pit_size_32bit);
sp804_pit_Timer1Control_timer_pre_wrf(pit, sp804_pit_prescale0);
sp804_pit_Timer1Control_int_enable_wrf(pit, 0);
sp804_pit_Timer1Control_timer_mode_wrf(pit, sp804_pit_periodic);
sp804_pit_Timer1Control_timer_en_wrf(pit, 0);
//configure timer 2
sp804_pit_Timer2Control_one_shot_wrf(pit, 0);
sp804_pit_Timer2Control_timer_size_wrf(pit, sp804_pit_size_32bit);
sp804_pit_Timer2Control_timer_pre_wrf(pit, sp804_pit_prescale0);
sp804_pit_Timer2Control_int_enable_wrf(pit, 0);
sp804_pit_Timer2Control_timer_mode_wrf(pit, sp804_pit_periodic);
sp804_pit_Timer2Control_timer_en_wrf(pit, 0);
// enable PIT interrupt
uint32_t int_id = pit_id ? PIT1_IRQ : PIT0_IRQ;
gic_enable_interrupt(int_id, 0x1, 0xf, 0x1, 0);
}