void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
{
gic_set_irq_priority(irq_id, priority);
gic_set_irq_security(irq_id, false); // set IRQ as non-secure
gic_set_cpu_target(irq_id, cpu_id, true);
gic_enable_irq(irq_id, true);
}
void sp804_enable()
{
sp804_init();
writel(0xE2, TIMER1_CONTROL(TIMER1_BASE));
register_irq_handler(34, &sp804_handler);
gic_configure_irq(34, IRQ_LEVEL_TRIGGERED);
gic_enable_irq(34);
}
hvmm_status_t gic_configure_irq(uint32_t irq,
enum gic_int_polarity polarity, uint8_t cpumask,
uint8_t priority)
{
hvmm_status_t result = HVMM_STATUS_UNKNOWN_ERROR;
HVMM_TRACE_ENTER();
if (irq < _gic.lines) {
uint32_t icfg;
volatile uint8_t *reg8;
/* disable forwarding */
result = gic_disable_irq(irq);
if (result == HVMM_STATUS_SUCCESS) {
/* polarity: level or edge */
icfg = _gic.ba_gicd[GICD_ICFGR + irq / 16];
if (polarity == GIC_INT_POLARITY_LEVEL)
icfg &= ~(2u << (2 * (irq % 16)));
else
icfg |= (2u << (2 * (irq % 16)));
_gic.ba_gicd[GICD_ICFGR + irq / 16] = icfg;
/* routing */
reg8 = (uint8_t *) &(_gic.ba_gicd[GICD_ITARGETSR]);
reg8[irq] = cpumask;
/* priority */
reg8 = (uint8_t *) &(_gic.ba_gicd[GICD_IPRIORITYR]);
reg8[irq] = priority;
/* enable forwarding */
result = gic_enable_irq(irq);
}
} else {
uart_print("invalid irq:");
uart_print_hex32(irq);
uart_print("\n\r");
result = HVMM_STATUS_UNSUPPORTED_FEATURE;
}
HVMM_TRACE_EXIT();
return result;
}
void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
{
gic_enable_irq(irq_id, false);
gic_set_cpu_target(irq_id, cpu_id, false);
}
