/******************************************************************************* * Place the cpu interface in a state where it can never make a cpu exit wfi as * as result of an asserted interrupt. This is critical for powering down a cpu ******************************************************************************/ void gic_cpuif_deactivate(unsigned int gicc_base) { unsigned int val; /* Disable secure, non-secure interrupts and disable their bypass */ val = gicc_read_ctlr(gicc_base); val &= ~(ENABLE_GRP0 | ENABLE_GRP1); val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; gicc_write_ctlr(gicc_base, val); }
/******************************************************************************* * Place the cpu interface in a state where it can never make a cpu exit wfi as * as result of an asserted interrupt. This is critical for powering down a cpu ******************************************************************************/ void tegra_gic_cpuif_deactivate(void) { unsigned int val; /* Disable secure, non-secure interrupts and disable their bypass */ val = gicc_read_ctlr(TEGRA_GICC_BASE); val &= ~(ENABLE_GRP0 | ENABLE_GRP1); val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; gicc_write_ctlr(TEGRA_GICC_BASE, val); }
/******************************************************************************* * This function allows the interrupt management framework to determine (through * the platform) which interrupt line (IRQ/FIQ) to use for an interrupt type to * route it to EL3. The interrupt line is represented as the bit position of the * IRQ or FIQ bit in the SCR_EL3. ******************************************************************************/ uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type) { uint32_t gicc_ctlr; /* Non-secure interrupts are signalled on the IRQ line always */ if (type == INTR_TYPE_NS) return __builtin_ctz(SCR_IRQ_BIT); /* * Secure interrupts are signalled using the IRQ line if the FIQ_EN * bit is not set else they are signalled using the FIQ line. */ gicc_ctlr = gicc_read_ctlr(cpuif_base); if (gicc_ctlr & FIQ_EN) return __builtin_ctz(SCR_FIQ_BIT); else return __builtin_ctz(SCR_IRQ_BIT); }