/******************************************************************************* * Helper function to configure the default attributes of SPIs. ******************************************************************************/ void gicv2_spis_configure_defaults(uintptr_t gicd_base) { unsigned int index, num_ints; num_ints = gicd_read_typer(gicd_base); num_ints &= TYPER_IT_LINES_NO_MASK; num_ints = (num_ints + 1) << 5; /* * Treat all SPIs as G1NS by default. The number of interrupts is * calculated as 32 * (IT_LINES + 1). We do 32 at a time. */ for (index = MIN_SPI_ID; index < num_ints; index += 32) gicd_write_igroupr(gicd_base, index, ~0U); /* Setup the default SPI priorities doing four at a time */ for (index = MIN_SPI_ID; index < num_ints; index += 4) gicd_write_ipriorityr(gicd_base, index, GICD_IPRIORITYR_DEF_VAL); /* Treat all SPIs as level triggered by default, 16 at a time */ for (index = MIN_SPI_ID; index < num_ints; index += 16) gicd_write_icfgr(gicd_base, index, 0); }
void gicd_clr_igroupr(uintptr_t base, unsigned int id) { unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); unsigned int reg_val = gicd_read_igroupr(base, id); gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); }
/******************************************************************************* * Global gic distributor setup which will be done by the primary cpu after a * cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them. * It then enables the secure GIC distributor interface. ******************************************************************************/ static void tegra_gic_distif_setup(unsigned int gicd_base) { unsigned int index, num_ints; /* * Mark out non-secure interrupts. Calculate number of * IGROUPR registers to consider. Will be equal to the * number of IT_LINES */ num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; num_ints = (num_ints + 1) << 5; for (index = MIN_SPI_ID; index < num_ints; index += 32) gicd_write_igroupr(gicd_base, index, ~0); /* Setup SPI priorities doing four at a time */ for (index = MIN_SPI_ID; index < num_ints; index += 4) { gicd_write_ipriorityr(gicd_base, index, GICD_IPRIORITYR_DEF_VAL); } /* * Configure the SGI and PPI. This is done in a separated function * because each CPU is responsible for initializing its own private * interrupts. */ tegra_gic_pcpu_distif_setup(gicd_base); /* enable distributor */ gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1); }
/******************************************************************************* * Global gic distributor setup which will be done by the primary cpu after a * cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them. * It then enables the secure GIC distributor interface. ******************************************************************************/ static void tegra_gic_distif_setup(unsigned int gicd_base) { unsigned int ctr, num_ints; /* * Mark out non-secure interrupts. Calculate number of * IGROUPR registers to consider. Will be equal to the * number of IT_LINES */ num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; num_ints++; for (ctr = 0; ctr < num_ints; ctr++) gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0); /* enable distributor */ gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1); }
/******************************************************************************* * Helper function to configure secure G0 SGIs and PPIs. ******************************************************************************/ void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base, unsigned int num_ints, const unsigned int *sec_intr_list) { unsigned int index, irq_num, sec_ppi_sgi_mask = 0; /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ assert(num_ints ? (uintptr_t)sec_intr_list : 1); /* * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a * more scalable approach as it avoids clearing the enable bits in the * GICD_CTLR. */ gicd_write_icenabler(gicd_base, 0, ~0); /* Setup the default PPI/SGI priorities doing four at a time */ for (index = 0; index < MIN_SPI_ID; index += 4) gicd_write_ipriorityr(gicd_base, index, GICD_IPRIORITYR_DEF_VAL); for (index = 0; index < num_ints; index++) { irq_num = sec_intr_list[index]; if (irq_num < MIN_SPI_ID) { /* We have an SGI or a PPI. They are Group0 at reset */ sec_ppi_sgi_mask |= 1U << irq_num; /* Set the priority of this interrupt */ gicd_write_ipriorityr(gicd_base, irq_num, GIC_HIGHEST_SEC_PRIORITY); } } /* * Invert the bitmask to create a mask for non-secure PPIs and * SGIs. Program the GICD_IGROUPR0 with this bit mask. */ gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask); /* Enable the Group 0 SGIs and PPIs */ gicd_write_isenabler(gicd_base, 0, sec_ppi_sgi_mask); }
/******************************************************************************* * Per cpu gic distributor setup which will be done by all cpus after a cold * boot/hotplug. This marks out the secure interrupts & enables them. ******************************************************************************/ static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base) { unsigned int index, sec_ppi_sgi_mask = 0; assert(gicd_base); /* Setup PPI priorities doing four at a time */ for (index = 0; index < 32; index += 4) { gicd_write_ipriorityr(gicd_base, index, GICD_IPRIORITYR_DEF_VAL); } /* * Invert the bitmask to create a mask for non-secure PPIs and * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will * update the GICR_IGROUPR0 as well in case we are running on a GICv3 * system. This is critical if GICD_CTLR.ARE_NS=1. */ gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask); }