void gmacd_set_rx_callback(struct _gmacd* gmacd, uint8_t queue, gmacd_callback_t callback)
{
struct _gmacd_queue* q = &gmacd->queues[queue];
if (!callback) {
gmac_disable_it(gmacd->gmac, queue, GMAC_IDR_RCOMP);
q->rx_callback = NULL;
} else {
q->rx_callback = callback;
gmac_enable_it(gmacd->gmac, queue, GMAC_IER_RCOMP);
}
}
bool gmac_configure(Gmac* gmac)
{
pmc_enable_peripheral(get_gmac_id_from_addr(gmac));
/* Disable TX & RX and more */
gmac_set_network_control_register(gmac, 0);
gmac_set_network_config_register(gmac, GMAC_NCFGR_DBW_DBW32);
/* Disable interrupts */
gmac_disable_it(gmac, 0, ~0u);
#ifdef CONFIG_HAVE_GMAC_QUEUES
gmac_disable_it(gmac, 1, ~0u);
gmac_disable_it(gmac, 2, ~0u);
#endif
/* Clear statistics */
gmac_clear_statistics(gmac);
/* Clear all status bits in the receive status register. */
gmac_clear_rx_status(gmac, GMAC_RSR_RXOVR | GMAC_RSR_REC |
GMAC_RSR_BNA | GMAC_RSR_HNO);
/* Clear all status bits in the transmit status register */
gmac_clear_tx_status(gmac, GMAC_TSR_UBR | GMAC_TSR_COL |
GMAC_TSR_RLE | GMAC_TSR_TXGO | GMAC_TSR_TFC |
GMAC_TSR_TXCOMP | GMAC_TSR_UND | GMAC_TSR_HRESP);
/* Clear interrupts */
gmac_get_it_status(gmac, 0);
#ifdef CONFIG_HAVE_GMAC_QUEUES
gmac_get_it_status(gmac, 1);
gmac_get_it_status(gmac, 2);
#endif
return _gmac_configure_mdc_clock(gmac);
}
