static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) { u32 val = gtt_read(reg); val &= andmask; val |= ormask; gtt_write(reg, val); }
/* fill the palette. */ static void palette(void) { int i; unsigned long color = 0; for(i = 0; i < 256; i++, color += 0x010101){ gtt_write(_LGC_PALETTE_A + (i<<2),color); } }
static inline void gtt_write_regs(const struct gt_reg *gt) { for (; gt && gt->reg; gt++) { if (gt->andmask) gtt_rmw(gt->reg, gt->andmask, gt->ormask); else gtt_write(gt->reg, gt->ormask); } }
void mainboard_train_link(struct intel_dp *intel_dp) { u8 read_val; u8 link_status[DP_LINK_STATUS_SIZE]; gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011); intel_dp_get_training_pattern(intel_dp, &read_val); intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); intel_dp_get_lane_count(intel_dp, &read_val); intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0); intel_dp_get_link_status(intel_dp, link_status); gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2); intel_dp_get_training_pattern(intel_dp, &read_val); intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); intel_dp_get_link_status(intel_dp, link_status); intel_dp_get_lane_align_status(intel_dp, &read_val); intel_dp_get_training_pattern(intel_dp, &read_val); intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); }
/* On Haswell, DDI port buffers must be programmed with correct values * in advance. The buffer values are different for FDI and DP modes, * but the HDMI/DVI fields are shared among those. So we program the DDI * in either FDI or DP modes only, as HDMI connections will work with both * of those. */ static void intel_prepare_ddi_buffers(int port, int use_fdi_mode) { u32 reg; int i; u32 *ddi_translations = ((use_fdi_mode) ? hsw_ddi_translations_fdi : hsw_ddi_translations_dp); printk(BIOS_SPEW, "Initializing DDI buffers for port %d in %s mode\n", port, use_fdi_mode ? "FDI" : "DP"); for (i=0,reg=DDI_BUF_TRANS(port);i < ARRAY_SIZE(hsw_ddi_translations_fdi);i++) { gtt_write(reg,ddi_translations[i]); reg += 4; } }
static void igd_init(struct device *dev) { if (IS_ENABLED(CONFIG_GOP_SUPPORT)) return; /* IGD needs to be Bus Master */ u32 reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res || !gtt_res->base) return; /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { #if IS_ENABLED(CONFIG_CHROMEOS) if (developer_mode_enabled() || recovery_mode_enabled() || vboot_wants_oprom()) mdelay(CONFIG_PRE_GRAPHICS_DELAY); #else mdelay(CONFIG_PRE_GRAPHICS_DELAY); #endif } /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); #if IS_ENABLED(CONFIG_CHROMEOS) if (!gfx_get_init_done() && !acpi_is_wakeup_s3()) { /* * Enable DDI-A if the Option ROM did not execute: * * bit 0: Display detected (RO) * bit 4: DDI A supports 4 lanes and DDI E is not used * bit 7: DDI buffer is idle */ gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED); } #endif }
void mainboard_set_port_clk_dp(struct intel_dp *intel_dp) { u32 ddi_pll_sel = 0; switch (intel_dp->link_bw) { case DP_LINK_BW_1_62: ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; break; case DP_LINK_BW_2_7: ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; break; case DP_LINK_BW_5_4: ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; break; default: printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw); return; } gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel); }
static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; u32 reg32; /* Setup Panel Power On Delays */ reg32 = gtt_read(PP_ON_DELAYS); if (!reg32) { reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); gtt_write(PP_ON_DELAYS, reg32); } /* Setup Panel Power Off Delays */ reg32 = gtt_read(PP_OFF_DELAYS); if (!reg32) { reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); gtt_write(PP_OFF_DELAYS, reg32); } /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { reg32 = gtt_read(PP_DIVISOR); reg32 &= ~0x1f; reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; gtt_write(PP_DIVISOR, reg32); } /* Enable Backlight */ gtt_write(BLC_PWM_CTL2, (1 << 31)); if (conf->gfx.backlight == 0) gtt_write(BLC_PWM_CTL, 0x06100610); else gtt_write(BLC_PWM_CTL, conf->gfx.backlight); }
static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm) { for (; pm && pm->reg; pm++) gtt_write(bar, pm->reg, pm->value); }
static inline void gtt_write_powermeter(const struct gt_powermeter *pm) { for (; pm && pm->reg; pm++) gtt_write(pm->reg, pm->value); }
void runio(struct intel_dp *dp) { u8 read_val; intel_dp_wait_panel_power_control(0xabcd0008); /* vbios spins at this point. Some haswell weirdness? */ intel_dp_wait_panel_power_control(0xabcd0008); /* This should be a function like intel_panel_enable_backlight However, we are not sure how the value 0x3a9 comes up. It has to do something with PWM frequency */ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE); gtt_write(DEIIR,0x00008000); intel_dp_wait_reg(DEIIR, 0x00000000); gtt_write(DSPSTRIDE(dp->plane),dp->stride); intel_dp_sink_dpms(dp, 0); intel_dp_get_max_downspread(dp, &read_val); intel_dp_set_m_n_regs(dp); intel_dp_set_resolution(dp); gtt_write(PIPESRC(dp->pipe),dp->pipesrc); gtt_write(PIPECONF(dp->transcoder),0x00000000); gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000); mainboard_set_port_clk_dp(dp); gtt_write(DSPSTRIDE(dp->plane),dp->stride); gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888); gtt_write(DEIIR,0x00000080); gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags); gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN); intel_dp_wait_panel_power_control(0xabcd000a); /* what is this doing? Not sure yet. */ intel_dp_i2c_write(dp, 0x0); intel_dp_i2c_read(dp, &read_val); intel_dp_i2c_write(dp, 0x04); intel_dp_i2c_read(dp, &read_val); intel_dp_i2c_write(dp, 0x7e); intel_dp_i2c_read(dp, &read_val); /* this needs to be a call to a function */ gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091); gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091); /* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */ gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a); gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a); intel_dp_set_bw(dp); intel_dp_set_lane_count(dp); mainboard_train_link(dp); /* need a function: intel_ddi_set_tp or similar */ gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE); gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL); gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); gtt_write(BLC_PWM_PCH_CTL1,0x80000000); /* some of this is not needed. */ gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE ); gtt_write(SDEIIR,0x00000000); gtt_write(DEIIR,0x00000000); gtt_write(DEIIR,0x00008000); intel_dp_wait_reg(DEIIR, 0x00000000); gtt_write(DSPSTRIDE(dp->plane),dp->stride); gtt_write(PIPESRC(dp->pipe),dp->pipesrc); gtt_write(DEIIR,0x00000080); intel_dp_wait_reg(DEIIR, 0x00000000); gtt_write(DSPSTRIDE(dp->plane),dp->stride); gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON); gtt_write(SDEIIR,0x00000000); gtt_write(SDEIIR,0x00000000); gtt_write(DEIIR,0x00000000); }
static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_sandybridge_config *conf = dev->chip_info; u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); /* 15: Deassert Force Wake */ if (bridge_silicon_revision() < IVB_STEP_C0) { gtt_write(0xa18c, gtt_read(0xa18c) & ~1); gtt_poll(0x130090, (1 << 0), (0 << 0)); } else { gtt_write(0xa188, 0x1fffe); if (gtt_poll(0x130040, (1 << 0), (0 << 0))) gtt_write(0xa188, gtt_read(0xa188) | 1); } /* 16: SW RC Control */ gtt_write(0xa094, 0x00060000); /* Setup Digital Port Hotplug */ reg32 = gtt_read(0xc4030); if (!reg32) { reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; gtt_write(0xc4030, reg32); } /* Setup Panel Power On Delays */ reg32 = gtt_read(0xc7208); if (!reg32) { reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); gtt_write(0xc7208, reg32); } /* Setup Panel Power Off Delays */ reg32 = gtt_read(0xc720c); if (!reg32) { reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); gtt_write(0xc720c, reg32); } /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { reg32 = gtt_read(0xc7210); reg32 &= ~0xff; reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; gtt_write(0xc7210, reg32); } /* Enable Backlight if needed */ if (conf->gpu_cpu_backlight) { gtt_write(0x48250, (1 << 31)); gtt_write(0x48254, conf->gpu_cpu_backlight); } if (conf->gpu_pch_backlight) { gtt_write(0xc8250, (1 << 31)); gtt_write(0xc8254, conf->gpu_pch_backlight); } }
static void gma_pm_init_pre_vbios(struct device *dev) { u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init\n"); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res || !gtt_res->base) return; if (bridge_silicon_revision() < IVB_STEP_C0) { /* 1: Enable force wake */ gtt_write(0xa18c, 0x00000001); gtt_poll(0x130090, (1 << 0), (1 << 0)); } else { gtt_write(0xa180, 1 << 5); gtt_write(0xa188, 0xffff0001); gtt_poll(0x130040, (1 << 0), (1 << 0)); } if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ reg32 = gtt_read(0x42004); reg32 |= (1 << 14) | (1 << 15); gtt_write(0x42004, reg32); } if (bridge_silicon_revision() >= IVB_STEP_A0) { /* Display Reset Acknowledge Settings */ reg32 = gtt_read(0x45010); reg32 |= (1 << 1) | (1 << 0); gtt_write(0x45010, reg32); } /* 2: Get GT SKU from GTT+0x911c[13] */ reg32 = gtt_read(0x911c); if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { if (reg32 & (1 << 13)) { printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); gtt_write_powermeter(snb_pm_gt1); } else { printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n"); gtt_write_powermeter(snb_pm_gt2); } } else { u32 unit = MCHBAR32(0x5938) & 0xf; if (reg32 & (1 << 13)) { /* GT1 SKU */ printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt1); } else { /* GT2 SKU */ u32 tdp = MCHBAR32(0x5930) & 0x7fff; tdp /= (1 << unit); if (tdp <= 17) { /* <=17W ULV */ printk(BIOS_DEBUG, "IVB GT2 17W " "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_17w); } else if ((tdp >= 25) && (tdp <= 35)) { /* 25W-35W */ printk(BIOS_DEBUG, "IVB GT2 25W-35W " "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } else { /* All others */ printk(BIOS_DEBUG, "IVB GT2 35W " "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } } } /* 3: Gear ratio map */ gtt_write(0xa004, 0x00000010); /* 4: GFXPAUSE */ gtt_write(0xa000, 0x00070020); /* 5: Dynamic EU trip control */ gtt_write(0xa080, 0x00000004); /* 6: ECO bits */ reg32 = gtt_read(0xa180); reg32 |= (1 << 26) | (1 << 31); /* (bit 20=1 for SNB step D1+ / IVB A0+) */ if (bridge_silicon_revision() >= SNB_STEP_D1) reg32 |= (1 << 20); gtt_write(0xa180, reg32); /* 6a: for SnB step D2+ only */ if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && (bridge_silicon_revision() >= SNB_STEP_D2)) { reg32 = gtt_read(0x9400); reg32 |= (1 << 7); gtt_write(0x9400, reg32); reg32 = gtt_read(0x941c); reg32 &= 0xf; reg32 |= (1 << 1); gtt_write(0x941c, reg32); gtt_poll(0x941c, (1 << 1), (0 << 1)); } if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { reg32 = gtt_read(0x907c); reg32 |= (1 << 16); gtt_write(0x907c, reg32); /* 6b: Clocking reset controls */ gtt_write(0x9424, 0x00000001); } else { /* 6b: Clocking reset controls */ gtt_write(0x9424, 0x00000000); } /* 7 */ if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { gtt_write(0x138128, 0x00000029); /* Mailbox Data */ gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ if (gtt_poll(0x138124, (1 << 31), (0 << 31))) gtt_write(0x138124, 0x8000000a); gtt_poll(0x138124, (1 << 31), (0 << 31)); } /* 8 */ gtt_write(0xa090, 0x00000000); /* RC Control */ gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ /* 9 */ gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */ gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */ /* 10 */ gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ /* 11 */ gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ gtt_write(0xa068, 0x000186a0); /* RP Up EI */ gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ /* 11a: Enable Render Standby (RC6) */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { /* * IvyBridge should also support DeepRenderStandby. * * Unfortunately it does not work reliably on all SKUs so * disable it here and it can be enabled by the kernel. */ gtt_write(0xa090, 0x88040000); /* HW RC Control */ } else { gtt_write(0xa090, 0x88040000); /* HW RC Control */ } /* 12: Normal Frequency Request */ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ /* only the lower 7 bits are used and shifted left by 25 */ reg32 = MCHBAR32(0x5998); reg32 >>= 16; reg32 &= 0x7f; reg32 <<= 25; gtt_write(0xa008, reg32); /* 13: RP Control */ gtt_write(0xa024, 0x00000592); /* 14: Enable PM Interrupts */ gtt_write(0x4402c, 0x03000076); /* Clear 0x6c024 [8:6] */ reg32 = gtt_read(0x6c024); reg32 &= ~0x000001c0; gtt_write(0x6c024, reg32); /* Initialize DP buffer translation with recommended defaults */ gtt_write(0xe4f00, 0x0100030c); gtt_write(0xe4f04, 0x00b8230c); gtt_write(0xe4f08, 0x06f8930c); gtt_write(0xe4f0c, 0x05f8e38e); gtt_write(0xe4f10, 0x00b8030c); gtt_write(0xe4f14, 0x0b78830c); gtt_write(0xe4f18, 0x09f8d3cf); gtt_write(0xe4f1c, 0x01e8030c); gtt_write(0xe4f20, 0x09f863cf); gtt_write(0xe4f24, 0x0ff803cf); }