/** * intel_vgpu_decode_cursor_plane - Decode sprite plane * @vgpu: input vgpu * @plane: cursor plane to save decoded info * This function is called for decoding plane * * Returns: * 0 on success, non-zero if failed. */ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, struct intel_vgpu_cursor_plane_format *plane) { u32 val, mode, index; u32 alpha_plane, alpha_force; struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; int pipe; pipe = get_active_pipe(vgpu); if (pipe >= I915_MAX_PIPES) return -ENODEV; val = vgpu_vreg_t(vgpu, CURCNTR(pipe)); mode = val & MCURSOR_MODE; plane->enabled = (mode != MCURSOR_MODE_DISABLE); if (!plane->enabled) return -ENODEV; index = cursor_mode_to_drm(mode); if (!cursor_pixel_formats[index].bpp) { gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode); return -EINVAL; } plane->mode = mode; plane->bpp = cursor_pixel_formats[index].bpp; plane->drm_format = cursor_pixel_formats[index].drm_format; plane->width = cursor_pixel_formats[index].width; plane->height = cursor_pixel_formats[index].height; alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >> _CURSOR_ALPHA_PLANE_SHIFT; alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >> _CURSOR_ALPHA_FORCE_SHIFT; if (alpha_plane || alpha_force) gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", alpha_plane, alpha_force); plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) return -EINVAL; plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n", plane->base); return -EINVAL; } val = vgpu_vreg_t(vgpu, CURPOS(pipe)); plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT; plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT; plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)); return 0; }
/** * intel_vgpu_emulate_mmio_write - emulate MMIO write * @vgpu: a vGPU * @pa: guest physical address * @p_data: write data buffer * @bytes: access data length * * Returns: * Zero on success, negative error code if failed */ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa, void *p_data, unsigned int bytes) { struct intel_gvt *gvt = vgpu->gvt; unsigned int offset = 0; int ret = -EINVAL; if (vgpu->failsafe) { failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false); return 0; } mutex_lock(&vgpu->vgpu_lock); offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); if (WARN_ON(bytes > 8)) goto err; if (reg_is_gtt(gvt, offset)) { if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8))) goto err; if (WARN_ON(bytes != 4 && bytes != 8)) goto err; if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1))) goto err; ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset, p_data, bytes); if (ret) goto err; goto out; } if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) { ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes); goto out; } ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false); if (ret < 0) goto err; intel_gvt_mmio_set_accessed(gvt, offset); ret = 0; goto out; err: gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset, bytes); out: mutex_unlock(&vgpu->vgpu_lock); return ret; }
/** * intel_vgpu_emulate_opregion_request - emulating OpRegion request * @vgpu: a vGPU * @swsci: SWSCI request * * Returns: * Zero on success, negative error code if failed */ int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci) { u32 *scic, *parm; u32 func, subfunc; scic = vgpu_opregion(vgpu)->va + INTEL_GVT_OPREGION_SCIC; parm = vgpu_opregion(vgpu)->va + INTEL_GVT_OPREGION_PARM; if (!(swsci & SWSCI_SCI_SELECT)) { gvt_vgpu_err("requesting SMI service\n"); return 0; } /* ignore non 0->1 trasitions */ if ((vgpu_cfg_space(vgpu)[INTEL_GVT_PCI_SWSCI] & SWSCI_SCI_TRIGGER) || !(swsci & SWSCI_SCI_TRIGGER)) { return 0; } func = GVT_OPREGION_FUNC(*scic); subfunc = GVT_OPREGION_SUBFUNC(*scic); if (!querying_capabilities(*scic)) { gvt_vgpu_err("requesting runtime service: func \"%s\"," " subfunc \"%s\"\n", opregion_func_name(func), opregion_subfunc_name(subfunc)); /* * emulate exit status of function call, '0' means * "failure, generic, unsupported or unknown cause" */ *scic &= ~OPREGION_SCIC_EXIT_MASK; return 0; } *scic = 0; *parm = 0; return 0; }
static int map_vgpu_opregion(struct intel_vgpu *vgpu, bool map) { u64 mfn; int i, ret; for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) { mfn = intel_gvt_hypervisor_virt_to_mfn(vgpu_opregion(vgpu)->va + i * PAGE_SIZE); if (mfn == INTEL_GVT_INVALID_ADDR) { gvt_vgpu_err("fail to get MFN from VA\n"); return -EINVAL; } ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, vgpu_opregion(vgpu)->gfn[i], mfn, 1, map); if (ret) { gvt_vgpu_err("fail to map GFN to MFN, errno: %d\n", ret); return ret; } } return 0; }
/** * intel_vgpu_decode_sprite_plane - Decode sprite plane * @vgpu: input vgpu * @plane: sprite plane to save decoded info * This function is called for decoding plane * * Returns: * 0 on success, non-zero if failed. */ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, struct intel_vgpu_sprite_plane_format *plane) { u32 val, fmt; u32 color_order, yuv_order; int drm_format; int pipe; pipe = get_active_pipe(vgpu); if (pipe >= I915_MAX_PIPES) return -ENODEV; val = vgpu_vreg_t(vgpu, SPRCTL(pipe)); plane->enabled = !!(val & SPRITE_ENABLE); if (!plane->enabled) return -ENODEV; plane->tiled = !!(val & SPRITE_TILED); color_order = !!(val & SPRITE_RGB_ORDER_RGBX); yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >> _SPRITE_YUV_ORDER_SHIFT; fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT; if (!sprite_pixel_formats[fmt].bpp) { gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); return -EINVAL; } plane->hw_format = fmt; plane->bpp = sprite_pixel_formats[fmt].bpp; drm_format = sprite_pixel_formats[fmt].drm_format; /* Order of RGB values in an RGBxxx buffer may be ordered RGB or * BGR depending on the state of the color_order field */ if (!color_order) { if (drm_format == DRM_FORMAT_XRGB2101010) drm_format = DRM_FORMAT_XBGR2101010; else if (drm_format == DRM_FORMAT_XRGB8888) drm_format = DRM_FORMAT_XBGR8888; } if (drm_format == DRM_FORMAT_YUV422) { switch (yuv_order) { case 0: drm_format = DRM_FORMAT_YUYV; break; case 1: drm_format = DRM_FORMAT_UYVY; break; case 2: drm_format = DRM_FORMAT_YVYU; break; case 3: drm_format = DRM_FORMAT_VYUY; break; default: /* yuv_order has only 2 bits */ break; } } plane->drm_format = drm_format; plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) return -EINVAL; plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n", plane->base); return -EINVAL; } plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) & _SPRITE_STRIDE_MASK; val = vgpu_vreg_t(vgpu, SPRSIZE(pipe)); plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >> _SPRITE_SIZE_HEIGHT_SHIFT; plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >> _SPRITE_SIZE_WIDTH_SHIFT; plane->height += 1; /* raw height is one minus the real value */ plane->width += 1; /* raw width is one minus the real value */ val = vgpu_vreg_t(vgpu, SPRPOS(pipe)); plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT; plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT; val = vgpu_vreg_t(vgpu, SPROFFSET(pipe)); plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >> _SPRITE_OFFSET_START_X_SHIFT; plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >> _SPRITE_OFFSET_START_Y_SHIFT; return 0; }
/** * intel_vgpu_decode_primary_plane - Decode primary plane * @vgpu: input vgpu * @plane: primary plane to save decoded info * This function is called for decoding plane * * Returns: * 0 on success, non-zero if failed. */ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, struct intel_vgpu_primary_plane_format *plane) { u32 val, fmt; struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; int pipe; pipe = get_active_pipe(vgpu); if (pipe >= I915_MAX_PIPES) return -ENODEV; val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); plane->enabled = !!(val & DISPLAY_PLANE_ENABLE); if (!plane->enabled) return -ENODEV; if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)) { plane->tiled = val & PLANE_CTL_TILED_MASK; fmt = skl_format_to_drm( val & PLANE_CTL_FORMAT_MASK, val & PLANE_CTL_ORDER_RGBX, val & PLANE_CTL_ALPHA_MASK, val & PLANE_CTL_YUV422_ORDER_MASK); if (fmt >= ARRAY_SIZE(skl_pixel_formats)) { gvt_vgpu_err("Out-of-bounds pixel format index\n"); return -EINVAL; } plane->bpp = skl_pixel_formats[fmt].bpp; plane->drm_format = skl_pixel_formats[fmt].drm_format; } else { plane->tiled = val & DISPPLANE_TILED; fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK); plane->bpp = bdw_pixel_formats[fmt].bpp; plane->drm_format = bdw_pixel_formats[fmt].drm_format; } if (!plane->bpp) { gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); return -EINVAL; } plane->hw_format = fmt; plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) return -EINVAL; plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n", plane->base); return -EINVAL; } plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled, (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)) ? (_PRI_PLANE_STRIDE_MASK >> 6) : _PRI_PLANE_STRIDE_MASK, plane->bpp); plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> _PIPE_H_SRCSZ_SHIFT; plane->width += 1; plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; plane->height += 1; /* raw height is one minus the real value */ val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe)); plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> _PRI_PLANE_X_OFF_SHIFT; plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> _PRI_PLANE_Y_OFF_SHIFT; return 0; }