void
cyg_hal_platform_hardware_init(void)
{
hal_if_init(); // Initialize GDB[ROM]/eCos interfaces
show_led(' ');
show_led(' ');
}
//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
// Basic hardware initialization has already taken place
hal_if_init(); // Initialize logical I/O layer (virtual vector support)
}
void hal_hardware_init(void)
{
// Reset all interrupts
//
// Flush internal priority level stack
//
// Set up eCos/ROM interfaces
#if (defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_A) || \
(CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0)
hal_mac7100_esci_pins(FREESCALE_ESCI_A_I);
#endif
#if (defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_B) || \
(CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1)
hal_mac7100_esci_pins(FREESCALE_ESCI_B_I);
#endif
#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_C
hal_mac7100_esci_pins(FREESCALE_ESCI_C_I);
#endif
#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_D
hal_mac7100_esci_pins(FREESCALE_ESCI_D_I);
#endif
hal_intc_init(); // Initialize interrupt controller
hal_pit_init(); // Initilaize CLOCK for channels 1..10
hal_if_init();
}
void hal_hardware_init(void)
{
#ifndef CYGHWR_GBAX_VERSION_1_1
volatile unsigned long *psrc, *pdest;
int i;
#endif
// clear flags, set master interrupt enable
GBA_REG_IF = 0xffff;
GBA_REG_IE = 0;
GBA_REG_IME = 1;
// Set up eCos/ROM interfaces
hal_if_init();
hal_diag_register_mangler();
#if !defined(CYGHWR_GBAX_VERSION_1_1) && defined(CYG_HAL_STARTUP_ROM)
// copy patch vector code for illegal instruction into RAM
pdest = (volatile unsigned long *)XP_BRAM_START;
psrc = (volatile unsigned long *)hal_patch_vector_code;
for (i=0; i<128; i++)
pdest[i] = psrc[i];
#if 0
for (i=0; i<128; i++)
if (pdest[i] != psrc[i])
TD_Print("Error: RAM not present.");
#endif
#endif
}
void
hal_hardware_init(void)
{
hal_xscale_core_init();
// all interrupt sources to IRQ and disabled
*IXP425_INTR_SEL = 0;
*IXP425_INTR_EN = 0;
// Enable caches
HAL_DCACHE_ENABLE();
HAL_ICACHE_ENABLE();
// Let the timer run at a default rate (for delays)
hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
// Set up eCos/ROM interfaces
hal_if_init();
// Perform any platform specific initializations
plf_hardware_init();
#ifdef CYGPKG_IO_PCI
cyg_hal_plf_pci_init();
#endif
}
void hal_hardware_init(void)
{
hal_xscale_core_init();
*PXA2X0_ICMR = 0; // IRQ Mask
*PXA2X0_ICLR = 0; // Route interrupts to IRQ
*PXA2X0_ICCR = 1;
*PXA2X0_GRER0 = 0; // Disable rising edge detect
*PXA2X0_GRER1 = 0;
*PXA2X0_GRER2 = 0;
*PXA2X0_GFER0 = 0; // Disable falling edge detect
*PXA2X0_GFER1 = 0;
*PXA2X0_GFER2 = 0;
*PXA2X0_GEDR0 = 0xffffffff; // Clear edge detect status
*PXA2X0_GEDR1 = 0xffffffff;
*PXA2X0_GEDR2 = 0x0001ffff;
plf_hardware_init(); // Perform any platform specific initializations
*PXA2X0_OSCR = 0; // Let the "OS" counter run
*PXA2X0_OSMR0 = 0;
hal_if_init(); // Set up eCos/ROM interfaces
HAL_DCACHE_ENABLE(); // Enable caches
HAL_ICACHE_ENABLE();
}
void
hal_platform_init(void)
{
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
hal_if_init();
#endif
}
void hal_hardware_init(void)
{
// Any hardware/platform initialization that needs to be done.
HAL_WRITE_UINT32(CYG_DEVICE_IRQ_EnableClear, 0xFFFF); // Clear all
// interrupt sources
// Set up eCos/ROM interfaces
hal_if_init();
}
void
hal_platform_init(void)
{
hal_if_init();
#if defined CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
HAL_DIAG_INIT();
#endif
}
void hal_platform_init(void)
{
hal_if_init();
// FIXME: Set up Galileo interrupt controller?
// Unmask vectors which are entry points for interrupt controllers
// HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_21555);
// HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_GALILEO);
}
// -------------------------------------------------------------------------
// Hardware init
void hal_hardware_init(void)
{
// Set up eCos/ROM interfaces
hal_if_init();
// Reset all interrupts
// All interrupts are enabled and masked
HAL_WRITE_UINT32(TIMER1_CTRL_REG, 0x4);
HAL_WRITE_UINT32(TIMER2_CTRL_REG, 0x4);
HAL_WRITE_UINT32(ICTL_MASK, ~(1<<CYGNUM_HAL_INTERRUPT_TIMER));
HAL_WRITE_UINT32(ICTL_ENABLE, 0xFFFFFFFF);
}
void hal_hardware_init(void)
{
volatile struct _gps4020_intc *intc = (volatile struct _gps4020_intc *)GPS4020_INTC;
// Clear and reset all interrupt sources
intc->enable = 0;
// 3322 2222 2222 1111 1111 1100 0000 0000
// 1098 7654 3210 9876 5432 1098 7654 3210
intc->polarity = 0x1C01E01F; // 0001 1100 0000 0001 1110 0000 0001 1111;
intc->trigger = 0x000C00C0; // 0000 0000 0000 1100 0000 0000 1100 0000;
// Set up eCos/ROM interfaces
hal_if_init();
}
void hal_reset(void)
{
// Do any variant-specific reset initialization
var_reset();
// Do any platform-specific reset initialization
plf_reset();
// Initialize the RAM sections that the rest of the C code requires
hal_init_ram_sections();
// All program sections are now in place
// Make sure that every instruction above this one has been output by
// the compiler
HAL_REORDER_BARRIER();
// Now it is safe to use a stack in RAM
asm volatile ("lea cyg_interrupt_stack, %sp");
// It is now safe to call C functions which may rely on initialized
// data
hal_vsr_init();
hal_isr_init();
// Initialize variant HAL private data
var_init_data();
// Initialize platform HAL private data
plf_init_data();
// Initialize the virtual vector table
hal_if_init();
// Call C++ constructors
cyg_hal_invoke_constructors();
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
initialize_stub();
#endif
// Init Ctrl-C debug ISR
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
hal_ctrlc_isr_init();
#endif
// Call cyg_start. This routine should not return.
cyg_start();
}
void
hal_platform_init(void)
{
HAL_WRITE_UINT32(AR531X_WDC, 0);
hal_ar5312_flash_setup();
// Set up eCos/ROM interfaces
hal_if_init();
HAL_ICACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_INVALIDATE_ALL();
HAL_DCACHE_ENABLE();
}
void hal_hardware_init(void)
{
#if 0
// Clear and initialize instruction cache
HAL_ICACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
#endif
// Any hardware/platform initialization that needs to be done.
// Reset all interrupt masks (disable all interrupt sources)
*(volatile cyg_uint8 *)CMA230_IMRw = 0;
*(volatile cyg_uint8 *)CMA230_CLR = 0xFF; // Clear all current interrupts
// Set up eCos/ROM interfaces
hal_if_init();
}
void
hal_platform_init(void)
{
/* Enable the Ethernet interrupt on the INTC on the CPU-board FPGA */
volatile cyg_uint32* const intDisableReg = (cyg_uint32*)FPGA_INTDSB_REG;
volatile cyg_uint32* const intPriorityReg = (cyg_uint32*)FPGA_INTPRI_REG(FPGA_ETHERNET_INT);
*intDisableReg = 0;
/* Set the interrupt priority level for the Ethenet chip on the FPGA */
*intPriorityReg &= ~FPGA_INTPRI_MASK(FPGA_ETHERNET_INT);
*intPriorityReg |= FPGA_INTPRI_LEVEL(FPGA_ETHERNET_INT,ETHERNET_INT_PRIORITY);
hal_if_init();
}
//--------------------------------------------------------------------------
void hal_variant_init(void)
{
// Initialize I/O interfaces
hal_if_init();
#if defined(CYGHWR_HAL_POWERPC_PPC4XX_405) || defined(CYGHWR_HAL_POWERPC_PPC4XX_405GP)
// Initialize I2C controller
hal_ppc405_i2c_init();
#endif
// Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
hal_ppc40x_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
#ifdef CYGPKG_IO_PCI
hal_ppc405_pci_init();
#endif
}
//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
/*----------------------------------------------------------------------*/
/* Enable RS232 interface on the VADS board via BCSR1. BCSR1 is a Board */
/* Control and Status Register that resides in a programmable logic */
/* device. */
/*----------------------------------------------------------------------*/
//*BCSR1 &= 0xFFFFFFFD; /* Assert the RS232EN_1/ bit */
/* The Pilot revision of the MPC8260ADS board has moved the 8 bits
* in the 32 bit BCSR0 and BCSR1 from D24-D31 to D0-D7.
*/
*BCSR1 &= 0xFDFFFFFF; /* Assert the RS232EN_1/ bit */
hal_if_init();
}
// -------------------------------------------------------------------------
// Hardware init
void hal_hardware_init(void)
{
cyg_uint32 intmask;
// Set up eCos/ROM interfaces
hal_if_init();
// Enable cache
HAL_WRITE_UINT32(E7T_SYSCFG,
0x07FFFF80|E7T_SYSCFG_CM_0R_8C|E7T_SYSCFG_WE);
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
// Clear global interrupt mask bit
HAL_READ_UINT32(E7T_INTMSK, intmask);
intmask &= ~E7T_INTMSK_GLOBAL;
HAL_WRITE_UINT32(E7T_INTMSK, intmask);
}
void hal_platform_init(void)
{
#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
// Set up eCos/ROM interfaces
hal_if_init();
#endif
#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
(defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon) || \
defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs))
{
extern CYG_ADDRESS hal_virtual_vector_table[32];
void patch_dbg_syscalls( void * );
patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) );
}
#endif
}
void
hal_platform_init(void)
{
// Init superIO before calling if_init (which will use UARTs)
cyg_hal_init_superIO();
hal_if_init();
#if defined(CYGPKG_REDBOOT) && defined(CYGPKG_IO_PCI)
cyg_hal_plf_pci_init();
#endif
// Set up interrupt arbiter
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_PCI, 1,
0, cyg_hal_plf_pci_arbiter, NULL,
&intr_handle, &intr);
cyg_drv_interrupt_attach(intr_handle);
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_PCI);
}
//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
cyg_uint32 bcsr, gcr, frr, eicr, iack;
int vec;
// Initialize I/O interfaces
hal_if_init();
// Reset interrupt controller/state
HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
HAL_READ_UINT32LE(_CSB281_EPIC_FRR, frr);
HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_R);
do {
HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
} while ((gcr & _CSB281_EPIC_GCR_R) != 0);
HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_M);
HAL_READ_UINT32LE(_CSB281_EPIC_EICR, eicr); // Force direct interrupts
eicr &= ~_CSB281_EPIC_EICR_SIE;
HAL_WRITE_UINT32LE(_CSB281_EPIC_EICR, eicr);
for (vec = CYGNUM_HAL_INTERRUPT_IRQ0; vec <= CYGNUM_HAL_ISR_MAX; vec++) {
HAL_INTERRUPT_CONFIGURE(vec, 0, 0); // Default to low-edge
HAL_INTERRUPT_SET_LEVEL(vec, 0x0F); // Priority
}
vec = (frr & 0x0FFF0000) >> 16; // Number of interrupt sources
while (vec-- > 0) {
HAL_READ_UINT32LE(_CSB281_EPIC_IACK, iack);
HAL_WRITE_UINT32LE(_CSB281_EPIC_EOI, 0);
}
HAL_WRITE_UINT32LE(_CSB281_EPIC_PCTPR, 1); // Enables interrupts
#ifndef CYGSEM_HAL_USE_ROM_MONITOR
// Reset peripherals
HAL_READ_UINT32(_CSB281_BCSR, bcsr);
HAL_WRITE_UINT32(_CSB281_BCSR, _zero_bit(bcsr, _CSB281_BCSR_PRESET));
HAL_WRITE_UINT32(_CSB281_BCSR, _one_bit(bcsr, _CSB281_BCSR_PRESET));
_csb281_i2c_init();
_csb281_fs6377_init(0);
#endif
#ifdef CYGSEM_CSB281_LCD_COMM
lcd_comm_init();
#endif
_csb281_pci_init();
}
void plf_hardware_init(void)
#endif
{
// Any hardware/platform initialization that needs to be done.
// Clear all interrupt sources
HAL_WRITE_UINT32(CYG_DEVICE_IRQ_EnableClear, 0xFFFF);
#ifndef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
#endif
// FIXME: The line with the thumb check is a hack, allowing
// the farm to run test. Problem is that virtual vector table
// API needs to be ARM/Thumb consistent. Will fix later.
#if !defined(__thumb__) && !defined(CYGPKG_HAL_ARM_INTEGRATOR_ARM9)
// Set up eCos/ROM interfaces
hal_if_init();
#endif
}
void hal_variant_init( void )
{
hal_update_clock_var();
#if defined CYGPKG_HAL_KINETIS_CACHE
# ifndef CYG_HAL_STARTUP_RAM
hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PS_P,
sizeof(cache_reg_modes)/sizeof(cache_reg_modes[0]),
cache_reg_modes);
hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PC_P,
sizeof(cache_reg_modes)/sizeof(cache_reg_modes[0]),
cache_reg_modes);
# endif
# ifdef ENABLE_CACHE_ON_STARTUP
HAL_DCACHE_ENABLE();
HAL_ICACHE_ENABLE();
# endif
#endif // defined CYGPKG_HAL_KINETIS_CACHE
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
hal_if_init();
#endif
}
//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
// Special routing information for CICR
eppc->cpmi_cicr &= ~0xFF0000; // Routing bits
eppc->cpmi_cicr |= 0x240000; // SCC2, SCC3 on "normal" bit positions
#if defined(CYGHWR_HAL_POWERPC_ADDER_I)
eppc->pip_pbpar &= ~0x0000400E; // PB29..30 AS GPIO
eppc->pip_pbdir |= 0x0000400E;
eppc->pip_pbdat = 0x00004000;
#endif
#if defined(CYGHWR_HAL_POWERPC_ADDER_II)
#if defined(CYGHWR_HAL_POWERPC_MPC8XX_852T)
// Special settings - according to manual errata
eppc->pio_papar &= ~0xffffffff; // PA manatory settings
eppc->pio_padir |= 0xffffffff;
eppc->pip_pbpar &= ~0x0003ff07; // PB29..31 AS GPIO
eppc->pip_pbdir |= 0x0003ff07;
eppc->pip_pbdat = 0x00010007;
eppc->pio_pcpar &= ~0xffffffff; // PC manatory settings
eppc->pio_pcdir |= 0xffffffff;
#endif
eppc->pip_pbpar &= ~0x00000007; // PB29..31 AS GPIO for LEDS
eppc->pip_pbdir |= 0x00000007;
eppc->pip_pbdat |= 0x00000007;
#endif
hal_if_init();
_adder_set_leds(0x1);
}
void hal_platform_init(void)
{
HAL_WRITE_UINT8(HAL_LED_ADDRESS, cyg_hal_plf_led_val(8));
#if defined(CYG_HAL_STARTUP_ROM)
// Note that the hardware seems to come up with the
// caches containing random data. Hence they must be
// invalidated before being enabled.
// However, we only do this if we are in ROM. If we are
// in RAM, then we leave the caches in the state chosen
// by the ROM monitor. If we enable them when the monitor
// is not expecting it, we can end up breaking things if the
// monitor is not doing cache flushes.
//HAL_ICACHE_INVALIDATE_ALL();
//HAL_ICACHE_ENABLE();
//HAL_DCACHE_INVALIDATE_ALL();
//HAL_DCACHE_ENABLE();
#endif
// Set up eCos/ROM interfaces
hal_if_init();
#if defined(CYGPKG_KERNEL) && \
defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
{
extern void patch_dbg_syscalls(void * vector);
patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) );
}
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
{
static void hal_ctrlc_isr_init(void);
hal_ctrlc_isr_init();
}
#endif
}
void hal_hardware_init(void)
{
// Any hardware/platform initialization that needs to be done.
// Set all unknowns as edge triggered
HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR0,
ICTL_ICR0_CH0_HL_AL|ICTL_ICR0_CH0_EL_ET|
ICTL_ICR0_CH1_HL_AL|ICTL_ICR0_CH1_EL_ET|
ICTL_ICR0_CH2_HL_AL|ICTL_ICR0_CH2_EL_ET|
ICTL_ICR0_CH3_HL_AL|ICTL_ICR0_CH3_EL_ET|
ICTL_ICR0_CH4_HL_AL|ICTL_ICR0_CH4_EL_ET|
ICTL_ICR0_CH5_HL_AL|ICTL_ICR0_CH5_EL_ET);
HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR1,
ICTL_ICR1_CH6_HL_AL|
ICTL_ICR1_CH7_HL_AL|
ICTL_ICR1_CH8_HL_AL);
HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, 0xFFFF); // CLear all interrupts
HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, 0x0000); // All disabled
// Clear and initialize cache
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
// Set up eCos/ROM interfaces
hal_if_init();
}
void hal_platform_init(void)
{
hal_if_init();
}
void hal_platform_init(void)
{
// Initialize I/O interfaces
hal_if_init();
}
/**
*
* Hardware initialization.
*
* @return none
*
*****************************************************************************/
void hal_hardware_init(void)
{
cyg_uint32 dw_i, dwCPUID;
// -------- Ininializing GIC -------------------------------------------
// Connect GIC to CORE0
dwCPUID = 1;
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR + XSCUGIC_DIST_EN_OFFSET, 0UL);
// For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
//
// 1. The trigger mode in the int_config register
// Only write to the SPI interrupts, so start at 32
//
for (dw_i = 32; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 16) {
//
// Each INT_ID uses two bits, or 16 INT_ID per register
// Set them all to be level sensitive, active HIGH.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_INT_CFG_OFFSET_CALC(dw_i),
0UL);
}
for (dw_i = 0; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 4) {
//
// 2. The priority using int the priority_level register
// The priority_level and spi_target registers use one byte per
// INT_ID.
// Write a default value that can be changed elsewhere.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_PRIORITY_OFFSET_CALC(dw_i),
DEFAULT_PRIORITY);
}
for (dw_i = 32; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 4) {
//
// 3. The CPU interface in the spi_target register
// Only write to the SPI interrupts, so start at 32
//
dwCPUID |= dwCPUID << 8;
dwCPUID |= dwCPUID << 16;
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_SPI_TARGET_OFFSET_CALC(dw_i),
dwCPUID);
}
for (dw_i = 0; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 32) {
//
// 4. Enable the SPI using the enable_set register. Leave all
// disabled for now.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, dw_i),
0xFFFFFFFFUL);
}
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR + XSCUGIC_DIST_EN_OFFSET,
XSCUGIC_EN_INT_MASK);
//
// Program the priority mask of the CPU using the Priority mask register
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_CPU_BASEADDR + XSCUGIC_CPU_PRIOR_OFFSET, 0xF0);
//
// If the CPU operates in both security domains, set parameters in the
// control_s register.
// 1. Set FIQen=1 to use FIQ for secure interrupts,
// 2. Program the AckCtl bit
// 3. Program the SBPR bit to select the binary pointer behavior
// 4. Set EnableS = 1 to enable secure interrupts
// 5. Set EnbleNS = 1 to enable non secure interrupts
//
//
// If the CPU operates only in the secure domain, setup the
// control_s register.
// 1. Set FIQen=1,
// 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts.
// Only enable the IRQ output unless secure interrupts are needed.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_CPU_BASEADDR + XSCUGIC_CONTROL_OFFSET, 0x07);
#ifdef HAL_PLF_HARDWARE_INIT
// Perform any platform specific initializations
HAL_PLF_HARDWARE_INIT();
#endif
#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
HAL_DCACHE_ENABLE(); // Enable DCache
#endif
#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
HAL_ICACHE_ENABLE(); // Enable ICache
#endif
// Set up eCos/ROM interfaces
hal_if_init();
HAL_CLOCK_INITIALIZE(CYGNUM_HAL_RTC_PERIOD);
#ifdef CYGPKG_HAL_SMP_SUPPORT
cyg_uint32 reg;
/* Disable the distributor */
HAL_READ_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
reg &= ~(0x2);
HAL_WRITE_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
/* Clear pending interrupts */
HAL_WRITE_UINT32(XC7Z_ICD_ICPR0_BASEADDR, 0xffffffff);
HAL_WRITE_UINT32(XC7Z_ICD_ICPR1_BASEADDR, 0xffffffff);
HAL_WRITE_UINT32(XC7Z_ICD_ICPR2_BASEADDR, 0xffffffff);
/* Re-enable the distributor */
HAL_READ_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
reg |= 0x2;
HAL_WRITE_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
/* Start the cpu */
cyg_hal_smp_init();
hal_interrupt_init_cpu();
cyg_hal_smp_cpu_start_first();
#endif
}
