static irqreturn_t arizona_irq_thread(int irq, void *data)
{
struct arizona *arizona = data;
unsigned int val;
int ret;
ret = pm_runtime_get_sync(arizona->dev);
if (ret < 0) {
dev_err(arizona->dev, "Failed to resume device: %d\n", ret);
return IRQ_NONE;
}
/* Always handle the AoD domain */
handle_nested_irq(arizona->virq[0]);
/*
* Check if one of the main interrupts is asserted and only
* check that domain if it is.
*/
ret = regmap_read(arizona->regmap, ARIZONA_IRQ_PIN_STATUS, &val);
if (ret == 0 && val & ARIZONA_IRQ1_STS) {
handle_nested_irq(arizona->virq[1]);
} else if (ret != 0) {
dev_err(arizona->dev, "Failed to read main IRQ status: %d\n",
ret);
}
pm_runtime_mark_last_busy(arizona->dev);
pm_runtime_put_autosuspend(arizona->dev);
return IRQ_HANDLED;
}
static void wcd9xxx_irq_dispatch(struct wcd9xxx_core_resource *wcd9xxx_res,
struct intr_data *irqdata)
{
int irqbit = irqdata->intr_num;
if (!wcd9xxx_res->codec_reg_write) {
pr_err("%s: codec read/write callback not defined\n",
__func__);
return;
}
if (irqdata->clear_first) {
wcd9xxx_nested_irq_lock(wcd9xxx_res);
wcd9xxx_res->codec_reg_write(wcd9xxx_res,
WCD9XXX_A_INTR_CLEAR0 + BIT_BYTE(irqbit),
BYTE_BIT_MASK(irqbit));
if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
wcd9xxx_res->codec_reg_write(wcd9xxx_res,
WCD9XXX_A_INTR_MODE, 0x02);
handle_nested_irq(phyirq_to_virq(wcd9xxx_res, irqbit));
wcd9xxx_nested_irq_unlock(wcd9xxx_res);
} else {
wcd9xxx_nested_irq_lock(wcd9xxx_res);
handle_nested_irq(phyirq_to_virq(wcd9xxx_res, irqbit));
wcd9xxx_res->codec_reg_write(wcd9xxx_res,
WCD9XXX_A_INTR_CLEAR0 + BIT_BYTE(irqbit),
BYTE_BIT_MASK(irqbit));
if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
wcd9xxx_res->codec_reg_write(wcd9xxx_res,
WCD9XXX_A_INTR_MODE, 0x02);
wcd9xxx_nested_irq_unlock(wcd9xxx_res);
}
}
static irqreturn_t arizona_irq_thread(int irq, void *data)
{
struct arizona *arizona = data;
bool poll;
unsigned int val, nest_irq;
int ret;
ret = pm_runtime_get_sync(arizona->dev);
if (ret < 0) {
dev_err(arizona->dev, "Failed to resume device: %d\n", ret);
return IRQ_NONE;
}
do {
poll = false;
if (arizona->aod_irq_chip)
handle_nested_irq(irq_find_mapping(arizona->virq, 0));
if (arizona->irq_chip) {
/*
* Check if one of the main interrupts is asserted and
* only check that domain if it is.
*/
ret = regmap_read(arizona->regmap,
ARIZONA_IRQ_PIN_STATUS,
&val);
if (ret == 0 && val & ARIZONA_IRQ1_STS) {
nest_irq = irq_find_mapping(arizona->virq, 1);
handle_nested_irq(nest_irq);
} else if (ret != 0) {
dev_err(arizona->dev,
"Failed to read main IRQ status: %d\n",
ret);
}
}
/*
* Poll the IRQ pin status to see if we're really done
* if the interrupt controller can't do it for us.
*/
if (!arizona->pdata.irq_gpio) {
break;
} else if (arizona->pdata.irq_flags & IRQF_TRIGGER_RISING &&
gpio_get_value_cansleep(arizona->pdata.irq_gpio)) {
poll = true;
} else if (arizona->pdata.irq_flags & IRQF_TRIGGER_FALLING &&
!gpio_get_value_cansleep(arizona->pdata.irq_gpio)) {
poll = true;
}
} while (poll);
pm_runtime_mark_last_busy(arizona->dev);
pm_runtime_put_autosuspend(arizona->dev);
return IRQ_HANDLED;
}
static irqreturn_t t0_g_det_thread(int irq, void *data)
{
struct wm1811_machine_priv *wm1811 = data;
struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(wm1811->codec);
struct snd_soc_codec *codec = wm8994->codec;
if (wm1811->get_g_det_value_f()) {
pr_info("%s: G_DET_N GPIO is High!!!!", __func__);
mutex_lock(&wm8994->accdet_lock);
snd_soc_update_bits(codec, WM8958_MICBIAS2,
WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
/* Enable debounce while removed */
snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
WM1811_JACKDET_DB, WM1811_JACKDET_DB);
wm8994->mic_detecting = false;
wm8994->jack_mic = false;
snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
WM8958_MICD_ENA, 0);
t0_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
mutex_unlock(&wm8994->accdet_lock);
mutex_lock(&codec->mutex);
snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
snd_soc_dapm_sync(&codec->dapm);
mutex_unlock(&codec->mutex);
snd_soc_jack_report(wm8994->micdet[0].jack, 0,
SND_JACK_MECHANICAL | SND_JACK_HEADSET |
wm8994->btn_mask);
} else {
pr_info("%s: G_DET_N GPIO is Low!!!!", __func__);
handle_nested_irq(WM1811_JACKDET_IRQ_NUM);
msleep(100);
handle_nested_irq(WM1811_MIC_IRQ_NUM);
}
return IRQ_HANDLED;
}
static irqreturn_t arizona_irq_thread(int irq, void *data)
{
struct arizona *arizona = data;
bool poll;
unsigned int val;
int ret;
ret = pm_runtime_get_sync(arizona->dev);
if (ret < 0) {
dev_err(arizona->dev, "Failed to resume device: %d\n", ret);
return IRQ_NONE;
}
do {
poll = false;
/* Always handle the AoD domain */
handle_nested_irq(arizona->virq[0]);
/*
* Check if one of the main interrupts is asserted and only
* check that domain if it is.
*/
ret = regmap_read(arizona->regmap, ARIZONA_IRQ_PIN_STATUS,
&val);
if (ret == 0 && val & ARIZONA_IRQ1_STS) {
handle_nested_irq(arizona->virq[1]);
} else if (ret != 0) {
dev_err(arizona->dev,
"Failed to read main IRQ status: %d\n", ret);
}
/*
* Poll the IRQ pin status to see if we're really done
* if the interrupt controller can't do it for us.
*/
if (!arizona->pdata.irq_gpio) {
break;
} else if (arizona->pdata.irq_flags & IRQF_TRIGGER_RISING &&
gpio_get_value_cansleep(arizona->pdata.irq_gpio)) {
poll = true;
} else if (arizona->pdata.irq_flags & IRQF_TRIGGER_FALLING &&
!gpio_get_value_cansleep(arizona->pdata.irq_gpio)) {
poll = true;
}
} while (poll);
pm_runtime_put(arizona->dev);
return IRQ_HANDLED;
}
static irqreturn_t tc3589x_irq(int irq, void *data)
{
struct tc3589x *tc3589x = data;
int status;
again:
status = tc3589x_reg_read(tc3589x, TC3589x_IRQST);
if (status < 0)
return IRQ_NONE;
while (status) {
int bit = __ffs(status);
handle_nested_irq(tc3589x->irq_base + bit);
status &= ~(1 << bit);
}
/*
* A dummy read or write (to any register) appears to be necessary to
* have the last interrupt clear (for example, GPIO IC write) take
* effect. In such a case, recheck for any interrupt which is still
* pending.
*/
status = tc3589x_reg_read(tc3589x, TC3589x_IRQST);
if (status)
goto again;
return IRQ_HANDLED;
}
static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
{
struct crystalcove_gpio *cg = data;
unsigned int p0, p1;
int pending;
int gpio;
unsigned int virq;
if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
regmap_read(cg->regmap, GPIO1IRQ, &p1))
return IRQ_NONE;
regmap_write(cg->regmap, GPIO0IRQ, p0);
regmap_write(cg->regmap, GPIO1IRQ, p1);
pending = p0 | p1 << 8;
for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
if (pending & BIT(gpio)) {
virq = irq_find_mapping(cg->chip.irqdomain, gpio);
handle_nested_irq(virq);
}
}
return IRQ_HANDLED;
}
static irqreturn_t adp5588_irq_handler(int irq, void *devid)
{
struct adp5588_gpio *dev = devid;
unsigned status, bank, bit, pending;
int ret;
status = adp5588_gpio_read(dev->client, INT_STAT);
if (status & ADP5588_GPI_INT) {
ret = adp5588_gpio_read_intstat(dev->client, dev->irq_stat);
if (ret < 0)
memset(dev->irq_stat, 0, ARRAY_SIZE(dev->irq_stat));
for (bank = 0, bit = 0; bank <= ADP5588_BANK(ADP5588_MAXGPIO);
bank++, bit = 0) {
pending = dev->irq_stat[bank] & dev->irq_mask[bank];
while (pending) {
if (pending & (1 << bit)) {
handle_nested_irq(dev->irq_base +
(bank << 3) + bit);
pending &= ~(1 << bit);
}
bit++;
}
}
}
adp5588_gpio_write(dev->client, INT_STAT, status); /* Status is W1C */
return IRQ_HANDLED;
}
static irqreturn_t wsa_irq_thread(int irq, void *data)
{
struct wsa_resource *wsa_res = data;
int i;
u8 status;
if (wsa_res == NULL) {
pr_err("%s: wsa_res is NULL\n", __func__);
return IRQ_HANDLED;
}
if (wsa_res->codec == NULL) {
pr_err("%s: codec pointer not registered\n", __func__);
if (ptr_codec == NULL) {
pr_err("%s: did not recieve valid codec pointer\n",
__func__);
return IRQ_HANDLED;
} else {
wsa_res->codec = ptr_codec;
}
}
status = snd_soc_read(wsa_res->codec, WSA881X_INTR_STATUS);
/* Apply masking */
status &= ~wsa_res->irq_masks_cur;
for (i = 0; i < wsa_res->num_irqs; i++) {
if (status & BYTE_BIT_MASK(i)) {
mutex_lock(&wsa_res->nested_irq_lock);
handle_nested_irq(phyirq_to_virq(wsa_res, i));
mutex_unlock(&wsa_res->nested_irq_lock);
}
}
return IRQ_HANDLED;
}
static irqreturn_t tc35892_irq(int irq, void *data)
{
struct tc35892 *tc35892 = data;
int status;
status = tc35892_reg_read(tc35892, TC35892_IRQST);
if (status < 0)
return IRQ_NONE;
while (status) {
int bit = __ffs(status);
handle_nested_irq(tc35892->irq_base + bit);
status &= ~(1 << bit);
}
/*
* A dummy read or write (to any register) appears to be necessary to
* have the last interrupt clear (for example, GPIO IC write) take
* effect.
*/
tc35892_reg_read(tc35892, TC35892_IRQST);
return IRQ_HANDLED;
}
static void __do_irq(struct kthread_work *work)
{
struct mcuio_soft_hc *shc =
container_of(work, struct mcuio_soft_hc, do_irq);
handle_nested_irq(shc->irqno);
}
static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
{
int real_irq;
int virt_irq;
struct modem_irq *mi = (struct modem_irq *)data;
/* Read modem side IRQ number from modem IRQ controller */
real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF;
virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq;
pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X "
"which will be 0x%X (%d) which translates to "
"virtual IRQ 0x%X (%d)!\n",
(u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET,
real_irq,
real_irq & 0xFF,
real_irq & 0xFF,
virt_irq,
virt_irq);
if (virt_irq != 0)
handle_nested_irq(virt_irq);
pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq);
return IRQ_HANDLED;
}
static irqreturn_t tps6586x_irq(int irq, void *data)
{
struct tps6586x *tps6586x = data;
u32 acks;
int ret = 0;
ret = tps6586x_reads(tps6586x->dev, TPS6586X_INT_ACK1,
sizeof(acks), (uint8_t *)&acks);
if (ret < 0) {
dev_err(tps6586x->dev, "failed to read interrupt status\n");
return IRQ_NONE;
}
acks = le32_to_cpu(acks);
while (acks) {
int i = __ffs(acks);
if (tps6586x->irq_en & (1 << i))
handle_nested_irq(tps6586x->irq_base + i);
acks &= ~(1 << i);
}
return IRQ_HANDLED;
}
static irqreturn_t wm8994_edge_irq(int irq, void *data)
{
struct wm8994 *wm8994 = data;
while (gpio_get_value_cansleep(wm8994->pdata.irq_gpio))
handle_nested_irq(irq_create_mapping(wm8994->edge_irq, 0));
return IRQ_HANDLED;
}
/*
* This is a threaded IRQ handler so can access I2C/SPI. Since the
* IRQ handler explicitly clears the IRQ it handles the IRQ line
* will be reasserted and the physical IRQ will be handled again if
* another interrupt is asserted while we run - in the normal course
* of events this is a rare occurrence so we save I2C/SPI reads. We're
* also assuming that it's rare to get lots of interrupts firing
* simultaneously so try to minimise I/O.
*/
static irqreturn_t tps65912_irq(int irq, void *irq_data)
{
struct tps65912 *tps65912 = irq_data;
u32 irq_sts;
u32 irq_mask;
u8 reg;
int i;
tps65912->read(tps65912, TPS65912_INT_STS, 1, ®);
irq_sts = reg;
tps65912->read(tps65912, TPS65912_INT_STS2, 1, ®);
irq_sts |= reg << 8;
tps65912->read(tps65912, TPS65912_INT_STS3, 1, ®);
irq_sts |= reg << 16;
tps65912->read(tps65912, TPS65912_INT_STS4, 1, ®);
irq_sts |= reg << 24;
tps65912->read(tps65912, TPS65912_INT_MSK, 1, ®);
irq_mask = reg;
tps65912->read(tps65912, TPS65912_INT_MSK2, 1, ®);
irq_mask |= reg << 8;
tps65912->read(tps65912, TPS65912_INT_MSK3, 1, ®);
irq_mask |= reg << 16;
tps65912->read(tps65912, TPS65912_INT_MSK4, 1, ®);
irq_mask |= reg << 24;
irq_sts &= ~irq_mask;
if (!irq_sts)
return IRQ_NONE;
for (i = 0; i < tps65912->irq_num; i++) {
if (!(irq_sts & (1 << i)))
continue;
handle_nested_irq(tps65912->irq_base + i);
}
/* Write the STS register back to clear IRQs we handled */
reg = irq_sts & 0xFF;
irq_sts >>= 8;
if (reg)
tps65912->write(tps65912, TPS65912_INT_STS, 1, ®);
reg = irq_sts & 0xFF;
irq_sts >>= 8;
if (reg)
tps65912->write(tps65912, TPS65912_INT_STS2, 1, ®);
reg = irq_sts & 0xFF;
irq_sts >>= 8;
if (reg)
tps65912->write(tps65912, TPS65912_INT_STS3, 1, ®);
reg = irq_sts & 0xFF;
if (reg)
tps65912->write(tps65912, TPS65912_INT_STS4, 1, ®);
return IRQ_HANDLED;
}
static irqreturn_t max77693_irq_thread(int irq, void *data)
{
struct max77693_dev *max77693 = data;
u8 irq_reg[MAX77693_IRQ_GROUP_NR] = {};
u8 irq_src;
int ret;
int i, cur_irq;
ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_INTSRC,
&irq_src);
if (ret < 0) {
dev_err(max77693->dev, "Failed to read interrupt source: %d\n",
ret);
return IRQ_NONE;
}
if (irq_src & MAX77693_IRQSRC_CHG)
/* CHG_INT */
ret = max77693_read_reg(max77693->regmap, MAX77693_CHG_REG_CHG_INT,
&irq_reg[CHG_INT]);
if (irq_src & MAX77693_IRQSRC_TOP)
/* TOPSYS_INT */
ret = max77693_read_reg(max77693->regmap,
MAX77693_PMIC_REG_TOPSYS_INT, &irq_reg[TOPSYS_INT]);
if (irq_src & MAX77693_IRQSRC_FLASH)
/* LED_INT */
ret = max77693_read_reg(max77693->regmap,
MAX77693_LED_REG_FLASH_INT, &irq_reg[LED_INT]);
if (irq_src & MAX77693_IRQSRC_MUIC)
/* MUIC INT1 ~ INT3 */
max77693_bulk_read(max77693->regmap_muic, MAX77693_MUIC_REG_INT1,
MAX77693_NUM_IRQ_MUIC_REGS, &irq_reg[MUIC_INT1]);
/* Apply masking */
for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
if (i >= MUIC_INT1 && i <= MUIC_INT3)
irq_reg[i] &= max77693->irq_masks_cur[i];
else
irq_reg[i] &= ~max77693->irq_masks_cur[i];
}
/* Report */
for (i = 0; i < MAX77693_IRQ_NR; i++) {
if (irq_reg[max77693_irqs[i].group] & max77693_irqs[i].mask) {
cur_irq = irq_find_mapping(max77693->irq_domain, i);
if (cur_irq)
handle_nested_irq(cur_irq);
}
}
return IRQ_HANDLED;
}
static irqreturn_t tps65910_irq(int irq, void *irq_data)
{
struct tps65910 *tps65910 = irq_data;
u32 irq_sts;
u32 irq_mask;
u8 reg;
int i;
tps65910->read(tps65910, TPS65910_INT_STS, 1, ®);
irq_sts = reg;
tps65910->read(tps65910, TPS65910_INT_STS2, 1, ®);
irq_sts |= reg << 8;
switch (tps65910_chip_id(tps65910)) {
case TPS65911:
tps65910->read(tps65910, TPS65910_INT_STS3, 1, ®);
irq_sts |= reg << 16;
}
tps65910->read(tps65910, TPS65910_INT_MSK, 1, ®);
irq_mask = reg;
tps65910->read(tps65910, TPS65910_INT_MSK2, 1, ®);
irq_mask |= reg << 8;
switch (tps65910_chip_id(tps65910)) {
case TPS65911:
tps65910->read(tps65910, TPS65910_INT_MSK3, 1, ®);
irq_mask |= reg << 16;
}
irq_sts &= ~irq_mask;
if (!irq_sts)
return IRQ_NONE;
for (i = 0; i < tps65910->irq_num; i++) {
if (!(irq_sts & (1 << i)))
continue;
handle_nested_irq(tps65910->irq_base + i);
}
/* */
reg = irq_sts & 0xFF;
irq_sts >>= 8;
tps65910->write(tps65910, TPS65910_INT_STS, 1, ®);
reg = irq_sts & 0xFF;
tps65910->write(tps65910, TPS65910_INT_STS2, 1, ®);
switch (tps65910_chip_id(tps65910)) {
case TPS65911:
reg = irq_sts >> 8;
tps65910->write(tps65910, TPS65910_INT_STS3, 1, ®);
}
return IRQ_HANDLED;
}
static irqreturn_t max77665_irq_thread(int irq, void *data)
{
struct max77665_dev *max77665 = data;
u8 irq_reg[MAX77665_IRQ_GROUP_NR] = {0};
u8 irq_src;
int ret;
int i;
ret = max77665_read_reg(max77665->i2c, MAX77665_PMIC_REG_INTSRC,
&irq_src);
if (ret < 0) {
dev_err(max77665->dev, "Failed to read interrupt source: %d\n",
ret);
return IRQ_NONE;
}
if (irq_src & MAX77665_IRQSRC_CHG)
/* CHG_INT */
ret = max77665_read_reg(max77665->i2c, MAX77665_CHG_REG_CHG_INT,
&irq_reg[CHG_INT]);
if (irq_src & MAX77665_IRQSRC_TOP)
/* TOPSYS_INT */
ret = max77665_read_reg(max77665->i2c,
MAX77665_PMIC_REG_TOPSYS_INT, &irq_reg[TOPSYS_INT]);
if (irq_src & MAX77665_IRQSRC_FLASH)
/* LED_INT */
ret = max77665_read_reg(max77665->i2c,
MAX77665_LED_REG_FLASH_INT, &irq_reg[LED_INT]);
if (irq_src & MAX77665_IRQSRC_MUIC) {
/* MUIC INT1 */
ret = max77665_read_reg(max77665->muic,
MAX77665_MUIC_REG_INT1, &irq_reg[MUIC_INT1]);
}
/* Apply masking */
for (i = 0; i < MAX77665_IRQ_GROUP_NR; i++) {
if(i == MUIC_INT1)
irq_reg[i] &= max77665->irq_masks_cur[i];
else
irq_reg[i] &= ~max77665->irq_masks_cur[i];
}
/* Report */
for (i = 0; i < MAX77665_IRQ_NR; i++) {
if (irq_reg[max77665_irqs[i].group] & max77665_irqs[i].mask)
handle_nested_irq(max77665->irq_base + i);
}
return IRQ_HANDLED;
}
static void wcd9xxx_irq_dispatch(struct wcd9xxx *wcd9xxx, int irqbit)
{
if ((irqbit <= WCD9XXX_IRQ_MBHC_INSERTION) &&
(irqbit >= WCD9XXX_IRQ_MBHC_REMOVAL)) {
wcd9xxx_nested_irq_lock(wcd9xxx);
wcd9xxx_reg_write(wcd9xxx, WCD9XXX_A_INTR_CLEAR0 +
BIT_BYTE(irqbit),
BYTE_BIT_MASK(irqbit));
if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
wcd9xxx_reg_write(wcd9xxx, WCD9XXX_A_INTR_MODE, 0x02);
handle_nested_irq(phyirq_to_virq(wcd9xxx, irqbit));
wcd9xxx_nested_irq_unlock(wcd9xxx);
} else {
wcd9xxx_nested_irq_lock(wcd9xxx);
handle_nested_irq(phyirq_to_virq(wcd9xxx, irqbit));
wcd9xxx_reg_write(wcd9xxx, WCD9XXX_A_INTR_CLEAR0 +
BIT_BYTE(irqbit),
BYTE_BIT_MASK(irqbit));
if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
wcd9xxx_reg_write(wcd9xxx, WCD9XXX_A_INTR_MODE, 0x02);
wcd9xxx_nested_irq_unlock(wcd9xxx);
}
}
static irqreturn_t pmic_irq_thread(int irq, void *data)
{
int i;
int pending;
mutex_lock(&pmic->irq_lock);
intel_mid_pmic_writeb(MIRQLVL1, (u8)pmic->irq_mask);
pending = intel_mid_pmic_readb(IRQLVL1) & (~pmic->irq_mask);
for (i = 0; i < PMIC_IRQ_NUM; i++)
if (pending & (1 << i))
handle_nested_irq(pmic->irq_base + i);
mutex_unlock(&pmic->irq_lock);
return IRQ_HANDLED;
}
static irqreturn_t max14577_irq_thread(int irq, void *data)
{
struct max14577_dev *max14577 = data;
struct max14577_platform_data *pdata = max14577->pdata;
u8 irq_reg[MAX14577_IRQ_REGS_NUM] = {0};
u8 tmp_irq_reg[MAX14577_IRQ_REGS_NUM] = {};
int gpio_val;
int i;
pr_debug("%s: irq gpio pre-state(0x%02x)\n", __func__,
gpio_get_value(pdata->irq_gpio));
do {
/* MAX14577 INT1 ~ INT3 */
max14577_bulk_read(max14577->i2c, MAX14577_REG_INT1,
MAX14577_IRQ_REGS_NUM,
&tmp_irq_reg[MAX14577_IRQ_INT1]);
/* Or temp irq register to irq register for if it retries */
for (i = MAX14577_IRQ_INT1; i < MAX14577_IRQ_REGS_NUM; i++)
irq_reg[i] |= tmp_irq_reg[i];
pr_info("%s: interrupt[1:0x%02x, 2:0x%02x, 3:0x%02x]\n",
__func__, irq_reg[MAX14577_IRQ_INT1],
irq_reg[MAX14577_IRQ_INT2], irq_reg[MAX14577_IRQ_INT3]);
gpio_val = gpio_get_value(pdata->irq_gpio);
pr_debug("%s: irq gpio post-state(0x%02x)\n", __func__,
gpio_val);
if (gpio_get_value(pdata->irq_gpio) == 0)
pr_warn("%s: irq_gpio is not High, retry read int reg\n",
__func__);
} while (gpio_val == 0);
/* Apply masking */
for (i = 0; i < MAX14577_IRQ_REGS_NUM; i++)
irq_reg[i] &= max14577->irq_masks_cur[i];
/* Report */
for (i = 0; i < MAX14577_IRQ_NUM; i++) {
if (irq_reg[max14577_irqs[i].group] & max14577_irqs[i].mask)
handle_nested_irq(pdata->irq_base + i);
}
return IRQ_HANDLED;
}
static void atc260x_onoff_irq_handle(struct atc260x_onoff_dev *atc260x_onoff)
{
if(atc260x_onoff->regdef->reg_reset_pnd != 0 && onoff_reset_irq > 0)
{
int ret;
struct atc260x_dev *atc260x = atc260x_onoff->atc260x;
const struct atc260x_onoff_regdef *regdef = atc260x_onoff->regdef;
ret = atc260x_reg_read(atc260x, regdef->reg_reset_pnd);
if(ret > 0 && (ret & regdef->reset_pnd_bitm) != 0)
{
handle_nested_irq(onoff_reset_irq);
pr_err("[onoff_reset_irq] %s: send irq!\n", __func__);
}
}
}
/*
* This is a threaded IRQ handler so can access I2C/SPI. Since all
* interrupts are clear on read the IRQ line will be reasserted and
* the physical IRQ will be handled again if another interrupt is
* asserted while we run - in the normal course of events this is a
* rare occurrence so we save I2C/SPI reads. We're also assuming that
* it's rare to get lots of interrupts firing simultaneously so try to
* minimise I/O.
*/
static irqreturn_t rk808_irq(int irq, void *irq_data)
{
struct rk808 *rk808 = irq_data;
u32 irq_sts;
u32 irq_mask;
u8 reg;
int i, cur_irq;
// printk("%s,line=%d\n", __func__,__LINE__);
wake_lock(&rk808->irq_wake);
rk808_i2c_read(rk808, RK808_INT_STS_REG1, 1, ®);
irq_sts = reg;
rk808_i2c_read(rk808, RK808_INT_STS_REG2, 1, ®);
irq_sts |= reg << 8;
rk808_i2c_read(rk808, RK808_INT_STS_MSK_REG1, 1, ®);
irq_mask = reg;
rk808_i2c_read(rk808, RK808_INT_STS_MSK_REG2, 1, ®);
irq_mask |= reg << 8;
irq_sts &= ~irq_mask;
if (!irq_sts)
{
wake_unlock(&rk808->irq_wake);
return IRQ_NONE;
}
for (i = 0; i < rk808->irq_num; i++) {
if (!(irq_sts & (1 << i)))
continue;
cur_irq = irq_find_mapping(rk808->irq_domain, i);
if (cur_irq)
handle_nested_irq(cur_irq);
}
/* Write the STS register back to clear IRQs we handled */
reg = irq_sts & 0xFF;
irq_sts >>= 8;
rk808_i2c_write(rk808, RK808_INT_STS_REG1, 1, reg);
reg = irq_sts & 0xFF;
rk808_i2c_write(rk808, RK808_INT_STS_REG2, 1, reg);
wake_unlock(&rk808->irq_wake);
return IRQ_HANDLED;
}
static irqreturn_t max77828_irq_thread(int irq, void *data)
{
struct max77828_dev *max77828 = data;
u8 irq_reg[MAX77828_IRQ_GROUP_NR] = {0};
u8 tmp_irq_reg[MAX77828_IRQ_GROUP_NR] = {};
int i;
pr_debug("%s: irq gpio pre-state(0x%02x)\n", __func__,
gpio_get_value(max77828->irq_gpio));
clear_retry:
max77828_bulk_read(max77828->muic, MAX77828_MUIC_REG_INT1,
MAX77828_NUM_IRQ_MUIC_REGS,
&tmp_irq_reg[MUIC_INT1]);
/* Or temp irq register to irq register for if it retries */
for (i = MUIC_INT1; i < MAX77828_IRQ_GROUP_NR; i++)
irq_reg[i] |= tmp_irq_reg[i];
pr_info("%s: muic interrupt(0x%02x, 0x%02x, 0x%02x)\n",
__func__, irq_reg[MUIC_INT1],
irq_reg[MUIC_INT2], irq_reg[MUIC_INT3]);
pr_debug("%s: irq gpio post-state(0x%02x)\n", __func__,
gpio_get_value(max77828->irq_gpio));
if (gpio_get_value(max77828->irq_gpio) == 0) {
pr_warn("%s: irq_gpio is not High!\n", __func__);
goto clear_retry;
}
/* Apply masking */
/*
for (i = 0; i < MAX77828_IRQ_GROUP_NR; i++) {
irq_reg[i] &= max77828->irq_masks_cur[i];
}
*/
/* Report */
for (i = 0; i < MAX77828_IRQ_NR; i++) {
if (irq_reg[max77828_irqs[i].group] & max77828_irqs[i].mask)
handle_nested_irq(max77828->irq_base + i);
}
return IRQ_HANDLED;
}
/*
* This is a threaded IRQ handler so can access I2C/SPI. Since all
* interrupts are clear on read the IRQ line will be reasserted and
* the physical IRQ will be handled again if another interrupt is
* asserted while we run - in the normal course of events this is a
* rare occurrence so we save I2C/SPI reads. We're also assuming that
* it's rare to get lots of interrupts firing simultaneously so try to
* minimise I/O.
*/
static irqreturn_t rk808_irq(int irq, void *irq_data)
{
struct rk808 *rk808 = irq_data;
u32 irq_sts;
u32 irq_mask;
u8 reg;
int i;
//printk(" rk808 irq %d \n",irq);
wake_lock(&rk808->irq_wake);
rk808_i2c_read(rk808, RK808_INT_STS_REG1, 1, ®);
irq_sts = reg;
rk808_i2c_read(rk808, RK808_INT_STS_REG2, 1, ®);
irq_sts |= reg << 8;
rk808_i2c_read(rk808, RK808_INT_STS_MSK_REG1, 1, ®);
irq_mask = reg;
rk808_i2c_read(rk808, RK808_INT_STS_MSK_REG2, 1, ®);
irq_mask |= reg << 8;
irq_sts &= ~irq_mask;
if (!irq_sts)
{
wake_unlock(&rk808->irq_wake);
return IRQ_NONE;
}
for (i = 0; i < rk808->irq_num; i++) {
if (!(irq_sts & (1 << i)))
continue;
handle_nested_irq(rk808->irq_base + i);
}
/* Write the STS register back to clear IRQs we handled */
reg = irq_sts & 0xFF;
irq_sts >>= 8;
rk808_i2c_write(rk808, RK808_INT_STS_REG1, 1, reg);
reg = irq_sts & 0xFF;
rk808_i2c_write(rk808, RK808_INT_STS_REG2, 1, reg);
wake_unlock(&rk808->irq_wake);
return IRQ_HANDLED;
}
static irqreturn_t max732x_irq_handler(int irq, void *devid)
{
struct max732x_chip *chip = devid;
uint8_t pending;
uint8_t level;
pending = max732x_irq_pending(chip);
if (!pending)
return IRQ_HANDLED;
do {
level = __ffs(pending);
handle_nested_irq(level + chip->irq_base);
pending &= ~(1 << level);
} while (pending);
return IRQ_HANDLED;
}
static irqreturn_t sec_pmic_irq_thread(int irq, void *data)
{
struct sec_pmic_dev *sec_pmic = data;
u8 irq_reg[NUM_IRQ_REGS-1];
int ret;
int i, reg_int1;
switch (sec_pmic->device_type) {
case S5M8763X:
case S5M8767X:
reg_int1 = S5M8767_REG_INT1;
break;
case S2MPS11X:
reg_int1 = S2MPS11_REG_INT1;
break;
default:
dev_err(sec_pmic->dev,
"Unknown device type %d\n",
sec_pmic->device_type);
return -EINVAL;
}
ret = sec_bulk_read(sec_pmic, reg_int1,
NUM_IRQ_REGS - 1, irq_reg);
if (ret < 0) {
dev_err(sec_pmic->dev, "Failed to read interrupt register: %d\n",
ret);
return IRQ_NONE;
}
for (i = 0; i < NUM_IRQ_REGS - 1; i++)
irq_reg[i] &= ~sec_pmic->irq_masks_cur[i];
for (i = 0; i < S2MPS11_IRQ_NR; i++) {
if (irq_reg[s2mps11_irqs[i].reg - 1] & s2mps11_irqs[i].mask)
handle_nested_irq(sec_pmic->irq_base + i);
}
return IRQ_HANDLED;
}
/*
* This is a threaded IRQ handler so can access I2C/SPI. Since all
* interrupts are clear on read the IRQ line will be reasserted and
* the physical IRQ will be handled again if another interrupt is
* asserted while we run - in the normal course of events this is a
* rare occurrence so we save I2C/SPI reads. We're also assuming that
* it's rare to get lots of interrupts firing simultaneously so try to
* minimise I/O.
*/
static irqreturn_t tps65910_irq(int irq, void *irq_data)
{
struct tps65910 *tps65910 = irq_data;
u16 irq_sts;
u16 irq_mask;
u8 reg;
int i;
tps65910->read(tps65910, TPS65910_INT_STS, 1, ®);
irq_sts = reg;
tps65910->read(tps65910, TPS65910_INT_STS2, 1, ®);
irq_sts |= reg << 8;
tps65910->read(tps65910, TPS65910_INT_MSK, 1, ®);
irq_mask = reg;
tps65910->read(tps65910, TPS65910_INT_MSK2, 1, ®);
irq_mask |= reg << 8;
irq_sts &= ~irq_mask;
if (!irq_sts)
return IRQ_NONE;
for (i = 0; i < TPS65910_NUM_IRQ; i++) {
if (!(irq_sts & (1 << i)))
continue;
handle_nested_irq(tps65910->irq_base + i);
}
/* Write the STS register back to clear IRQs we handled */
reg = irq_sts & 0xFF;
tps65910->write(tps65910, TPS65910_INT_STS, 1, ®);
reg = irq_sts >> 8;
tps65910->write(tps65910, TPS65910_INT_STS2, 1, ®);
return IRQ_HANDLED;
}
static irqreturn_t max77693_irq_thread(int irq, void *data)
{
struct max77693_dev *max77693 = data;
u8 irq_reg[MAX77693_IRQ_GROUP_NR] = {};
u8 irq_src;
int ret;
int i;
pr_debug("%s: irq gpio pre-state(0x%02x)\n", __func__,
gpio_get_value(max77693->irq_gpio));
clear_retry:
ret = max77693_read_reg(max77693->i2c,
MAX77693_PMIC_REG_INTSRC, &irq_src);
if (ret < 0) {
dev_err(max77693->dev, "Failed to read interrupt source: %d\n",
ret);
return IRQ_NONE;
}
pr_info("%s: interrupt source(0x%02x)\n", __func__, irq_src);
if (irq_src & MAX77693_IRQSRC_CHG) {
/* CHG_INT */
ret = max77693_read_reg(max77693->i2c, MAX77693_CHG_REG_CHG_INT,
&irq_reg[CHG_INT]);
pr_info("%s: charger interrupt(0x%02x)\n",
__func__, irq_reg[CHG_INT]);
}
if (irq_src & MAX77693_IRQSRC_TOP) {
/* TOPSYS_INT */
ret = max77693_read_reg(max77693->i2c,
MAX77693_PMIC_REG_TOPSYS_INT,
&irq_reg[TOPSYS_INT]);
pr_info("%s: topsys interrupt(0x%02x)\n",
__func__, irq_reg[TOPSYS_INT]);
}
if (irq_src & MAX77693_IRQSRC_FLASH) {
/* LED_INT */
ret = max77693_read_reg(max77693->i2c,
MAX77693_LED_REG_FLASH_INT,
&irq_reg[LED_INT]);
pr_info("%s: led interrupt(0x%02x)\n",
__func__, irq_reg[LED_INT]);
}
if (irq_src & MAX77693_IRQSRC_MUIC) {
/* MUIC INT1 ~ INT3 */
max77693_bulk_read(max77693->muic,
MAX77693_MUIC_REG_INT1,
MAX77693_NUM_IRQ_MUIC_REGS,
&irq_reg[MUIC_INT1]);
pr_info("%s: muic interrupt(0x%02x, 0x%02x, 0x%02x)\n",
__func__, irq_reg[MUIC_INT1],
irq_reg[MUIC_INT2], irq_reg[MUIC_INT3]);
}
pr_debug("%s: irq gpio post-state(0x%02x)\n", __func__,
gpio_get_value(max77693->irq_gpio));
if (gpio_get_value(max77693->irq_gpio) == 0) {
pr_warn("%s: irq_gpio is not High!\n", __func__);
goto clear_retry;
}
/* Apply masking */
for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
if (i >= MUIC_INT1 && i <= MUIC_INT3)
irq_reg[i] &= max77693->irq_masks_cur[i];
else
irq_reg[i] &= ~max77693->irq_masks_cur[i];
}
/* Report */
for (i = 0; i < MAX77693_IRQ_NR; i++) {
if (irq_reg[max77693_irqs[i].group] & max77693_irqs[i].mask)
handle_nested_irq(max77693->irq_base + i);
}
return IRQ_HANDLED;
}
static irqreturn_t max8997_irq_thread(int irq, void *data)
{
struct max8997_dev *max8997 = data;
u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
u8 irq_src;
int ret;
int i, cur_irq;
ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
if (ret < 0) {
dev_err(max8997->dev, "Failed to read interrupt source: %d\n",
ret);
return IRQ_NONE;
}
if (irq_src & MAX8997_IRQSRC_PMIC) {
/* PMIC INT1 ~ INT4 */
max8997_bulk_read(max8997->i2c, MAX8997_REG_INT1, 4,
&irq_reg[PMIC_INT1]);
}
if (irq_src & MAX8997_IRQSRC_FUELGAUGE) {
/*
* TODO: FUEL GAUGE
*
* This is to be supported by Max17042 driver. When
* an interrupt incurs here, it should be relayed to a
* Max17042 device that is connected (probably by
* platform-data). However, we do not have interrupt
* handling in Max17042 driver currently. The Max17042 IRQ
* driver should be ready to be used as a stand-alone device and
* a Max8997-dependent device. Because it is not ready in
* Max17042-side and it is not too critical in operating
* Max8997, we do not implement this in initial releases.
*/
irq_reg[FUEL_GAUGE] = 0;
}
if (irq_src & MAX8997_IRQSRC_MUIC) {
/* MUIC INT1 ~ INT3 */
max8997_bulk_read(max8997->muic, MAX8997_MUIC_REG_INT1, 3,
&irq_reg[MUIC_INT1]);
}
if (irq_src & MAX8997_IRQSRC_GPIO) {
/* GPIO Interrupt */
u8 gpio_info[MAX8997_NUM_GPIO];
irq_reg[GPIO_LOW] = 0;
irq_reg[GPIO_HI] = 0;
max8997_bulk_read(max8997->i2c, MAX8997_REG_GPIOCNTL1,
MAX8997_NUM_GPIO, gpio_info);
for (i = 0; i < MAX8997_NUM_GPIO; i++) {
bool interrupt = false;
switch (gpio_info[i] & MAX8997_GPIO_INT_MASK) {
case MAX8997_GPIO_INT_BOTH:
if (max8997->gpio_status[i] != gpio_info[i])
interrupt = true;
break;
case MAX8997_GPIO_INT_RISE:
if ((max8997->gpio_status[i] != gpio_info[i]) &&
(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
interrupt = true;
break;
case MAX8997_GPIO_INT_FALL:
if ((max8997->gpio_status[i] != gpio_info[i]) &&
!(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
interrupt = true;
break;
default:
break;
}
if (interrupt) {
if (i < 8)
irq_reg[GPIO_LOW] |= (1 << i);
else
irq_reg[GPIO_HI] |= (1 << (i - 8));
}
}
}
if (irq_src & MAX8997_IRQSRC_FLASH) {
/* Flash Status Interrupt */
ret = max8997_read_reg(max8997->i2c, MAX8997_REG_FLASHSTATUS,
&irq_reg[FLASH_STATUS]);
}
/* Apply masking */
for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++)
irq_reg[i] &= ~max8997->irq_masks_cur[i];
/* Report */
for (i = 0; i < MAX8997_IRQ_NR; i++) {
if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
cur_irq = irq_find_mapping(max8997->irq_domain, i);
if (cur_irq)
handle_nested_irq(cur_irq);
}
}
return IRQ_HANDLED;
}