void hsi_restore_ctx(struct hsi_dev *hsi_ctrl)
{
struct hsi_platform_data *pdata = hsi_ctrl->dev->platform_data;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
void __iomem *base = hsi_ctrl->base;
struct hsi_port_ctx *p;
int port;
hsi_outl(pdata->ctx->sysconfig, base, HSI_SYS_SYSCONFIG_REG);
hsi_outl(pdata->ctx->gdd_gcr, base, HSI_GDD_GCR_REG);
if (hsi_driver_device_is_hsi(pdev))
hsi_outl(pdata->ctx->dll, base, HSI_HSR_DLL_REG);
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx->pctx[port - 1];
/* HSI TOP */
hsi_outl(p->sys_mpu_enable[0], base,
HSI_SYS_MPU_ENABLE_REG(port, 0));
hsi_outl(p->sys_mpu_enable[1], base,
HSI_SYS_MPU_U_ENABLE_REG(port, 0));
/* HST */
hsi_outl(p->hst.mode, base, HSI_HST_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(p->hst.frame_size, base,
HSI_HST_FRAMESIZE_REG(port));
hsi_outl(p->hst.divisor, base, HSI_HST_DIVISOR_REG(port));
hsi_outl(p->hst.channels, base, HSI_HST_CHANNELS_REG(port));
hsi_outl(p->hst.arb_mode, base, HSI_HST_ARBMODE_REG(port));
/* HSR */
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(p->hsr.frame_size, base,
HSI_HSR_FRAMESIZE_REG(port));
hsi_outl(p->hsr.divisor, base, HSI_HSR_DIVISOR_REG(port));
hsi_outl(p->hsr.channels, base, HSI_HSR_CHANNELS_REG(port));
hsi_outl(p->hsr.counters, base, HSI_HSR_COUNTERS_REG(port));
}
if (hsi_driver_device_is_hsi(pdev)) {
/* SW strategy for HSI fifo management can be changed here */
hsi_fifo_mapping(hsi_ctrl, hsi_ctrl->fifo_mapping_strategy);
}
/* As a last step move HSR from MODE_VAL.SLEEP to the relevant mode. */
/* This will enable the ACREADY flow control mechanism. */
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx->pctx[port - 1];
hsi_outl(p->hsr.mode, base, HSI_HSR_MODE_REG(port));
}
}
void hsi_restore_ctx(struct hsi_dev *hsi_ctrl)
{
struct hsi_platform_data *pdata = hsi_ctrl->dev->platform_data;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
void __iomem *base = hsi_ctrl->base;
struct port_ctx *p;
int port;
hsi_outl(pdata->ctx->sysconfig, base, HSI_SYS_SYSCONFIG_REG);
hsi_outl(pdata->ctx->gdd_gcr, base, HSI_GDD_GCR_REG);
if (hsi_driver_device_is_hsi(pdev))
hsi_outl(pdata->ctx->dll, base, HSI_HSR_DLL_REG);
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx->pctx[port - 1];
/* HSI TOP */
hsi_outl(p->sys_mpu_enable[0], base,
HSI_SYS_MPU_ENABLE_REG(port, 0));
hsi_outl(p->sys_mpu_enable[1], base,
HSI_SYS_MPU_U_ENABLE_REG(port, 0));
/* HST */
hsi_outl(p->hst.mode, base, HSI_HST_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(p->hst.frame_size, base,
HSI_HST_FRAMESIZE_REG(port));
hsi_outl(p->hst.divisor, base, HSI_HST_DIVISOR_REG(port));
hsi_outl(p->hst.channels, base, HSI_HST_CHANNELS_REG(port));
hsi_outl(p->hst.arb_mode, base, HSI_HST_ARBMODE_REG(port));
/* HSR */
hsi_outl(p->hsr.mode, base, HSI_HSR_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(p->hsr.frame_size, base,
HSI_HSR_FRAMESIZE_REG(port));
hsi_outl(p->hsr.divisor, base, HSI_HSR_DIVISOR_REG(port));
hsi_outl(p->hsr.channels, base, HSI_HSR_CHANNELS_REG(port));
hsi_outl(p->hsr.counters, base, HSI_HSR_COUNTERS_REG(port));
}
if (hsi_driver_device_is_hsi(pdev)) {
/* SW strategy for HSI fifo management can be changed here */
hsi_fifo_mapping(hsi_ctrl, HSI_FIFO_MAPPING_DEFAULT);
}
}
static void hsi_set_ports_default(struct hsi_dev *hsi_ctrl,
struct platform_device *pd)
{
struct hsi_port_ctx *cfg;
struct hsi_platform_data *pdata = pd->dev.platform_data;
unsigned int port = 0;
void __iomem *base = hsi_ctrl->base;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
for (port = 1; port <= pdata->num_ports; port++) {
cfg = &pdata->ctx->pctx[port - 1];
/* HST */
hsi_outl(cfg->hst.mode | cfg->hst.flow |
HSI_HST_MODE_WAKE_CTRL_SW, base,
HSI_HST_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(cfg->hst.frame_size, base,
HSI_HST_FRAMESIZE_REG(port));
hsi_outl(cfg->hst.divisor, base, HSI_HST_DIVISOR_REG(port));
hsi_outl(cfg->hst.channels, base, HSI_HST_CHANNELS_REG(port));
hsi_outl(cfg->hst.arb_mode, base, HSI_HST_ARBMODE_REG(port));
/* HSR */
hsi_outl(cfg->hsr.mode | cfg->hsr.flow, base,
HSI_HSR_MODE_REG(port));
if (!hsi_driver_device_is_hsi(pdev))
hsi_outl(cfg->hsr.frame_size, base,
HSI_HSR_FRAMESIZE_REG(port));
hsi_outl(cfg->hsr.channels, base, HSI_HSR_CHANNELS_REG(port));
if (hsi_driver_device_is_hsi(pdev))
hsi_outl(cfg->hsr.divisor, base,
HSI_HSR_DIVISOR_REG(port));
hsi_outl(cfg->hsr.counters, base, HSI_HSR_COUNTERS_REG(port));
}
if (hsi_driver_device_is_hsi(pdev)) {
/* SW strategy for HSI fifo management can be changed here */
hsi_fifo_mapping(hsi_ctrl, hsi_ctrl->fifo_mapping_strategy);
hsi_outl(pdata->ctx->dll, base, HSI_HSR_DLL_REG);
}
}