static sw_error_t
garuda_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
{
hsl_port_prop_t p_type;
hsl_dev_t *pdev = NULL;
fal_port_t port_id;
pdev = hsl_dev_ptr_get(dev_id);
if (pdev == NULL)
return SW_NOT_INITIALIZED;
for (port_id = 0; port_id < pdev->nr_ports; port_id++)
{
hsl_port_prop_portmap_set(dev_id, port_id);
for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
{
if (HSL_NO_CPU == mode)
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
continue;
}
switch (p_type)
{
case HSL_PP_PHY:
if (HSL_CPU_1 != mode)
{
if ((port_id != pdev->cpu_port_nr)
&& (port_id != (pdev->nr_ports -1)))
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
}
else
{
if (port_id != pdev->cpu_port_nr)
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
}
break;
case HSL_PP_INCL_CPU:
/* include cpu port but exclude wan port in some cases */
if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
break;
case HSL_PP_EXCL_CPU:
/* exclude cpu port and wan port in some cases */
if ((port_id != pdev->cpu_port_nr)
&& (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))))
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
break;
default:
break;
}
}
if (HSL_NO_CPU == mode)
{
SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
(dev_id, port_id, port_id + 1));
}
else
{
if (port_id != pdev->cpu_port_nr)
{
SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
(dev_id, port_id, port_id - 1));
}
}
}
return SW_OK;
}
/* For isis there are five internal PHY devices and seven MAC devices.
MAC0 always connect to external MAC device.
PHY4 can connect to MAC5 or external MAC device.
MAC6 always connect to external devices.
MAC1..MAC4 connect to internal PHY0..PHY3.
*/
static sw_error_t
isis_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
{
hsl_port_prop_t p_type;
hsl_dev_t *pdev = NULL;
fal_port_t port_id;
pdev = hsl_dev_ptr_get(dev_id);
if (pdev == NULL)
return SW_NOT_INITIALIZED;
/* for port property set, SSDK should not generate some limitations */
for (port_id = 0; port_id < pdev->nr_ports; port_id++)
{
hsl_port_prop_portmap_set(dev_id, port_id);
for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
{
if (HSL_NO_CPU == mode)
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
continue;
}
switch (p_type)
{
case HSL_PP_PHY:
/* Only port0/port6 without PHY device */
if ((port_id != pdev->cpu_port_nr)
&& (port_id != pdev->nr_ports - 1))
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
break;
case HSL_PP_INCL_CPU:
/* include cpu port but exclude wan port in some cases */
/* but which port is wan port, we are no meaning */
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
break;
case HSL_PP_EXCL_CPU:
/* exclude cpu port and wan port in some cases */
/* which port is wan port, we are no meaning but port0 is
always CPU port */
if (port_id != pdev->cpu_port_nr)
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
break;
default:
break;
}
}
if (HSL_NO_CPU == mode)
{
SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
(dev_id, port_id, port_id + 1));
}
else
{
if (port_id != pdev->cpu_port_nr)
{
SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
(dev_id, port_id, port_id - 1));
}
}
}
return SW_OK;
}
static sw_error_t
dess_portproperty_init(a_uint32_t dev_id)
{
hsl_port_prop_t p_type;
hsl_dev_t *pdev = NULL;
fal_port_t port_id;
enum ssdk_port_wrapper_cfg cfg;
a_uint32_t bitmap = 0;
a_uint32_t phy_id;
pdev = hsl_dev_ptr_get(dev_id);
if (pdev == NULL)
return SW_NOT_INITIALIZED;
cfg = dess_get_port_config();
phy_id = dess_get_port_phy_id();
if (phy_id == MALIBU_1_1_2PORT)
bitmap = dess_pbmp_2[cfg];
else {
bitmap = dess_pbmp_5[cfg];
}
/* for port property set, SSDK should not generate some limitations */
for (port_id = 0; port_id < pdev->nr_ports; port_id++)
{
hsl_port_prop_portmap_set(dev_id, port_id);
for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
{
switch (p_type)
{
case HSL_PP_PHY:
/* Only port0 without PHY device */
if (port_id != pdev->cpu_port_nr)
{
if(SW_IS_PBMP_MEMBER(bitmap, port_id))
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
break;
case HSL_PP_INCL_CPU:
/* include cpu port but exclude wan port in some cases */
/* but which port is wan port, we are no meaning */
if (port_id == pdev->cpu_port_nr)
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
if(SW_IS_PBMP_MEMBER(bitmap, port_id))
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
break;
case HSL_PP_EXCL_CPU:
/* exclude cpu port and wan port in some cases */
/* which port is wan port, we are no meaning but port0 is
always CPU port */
if (port_id != pdev->cpu_port_nr)
{
if(SW_IS_PBMP_MEMBER(bitmap, port_id))
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
break;
default:
break;
}
}
if (port_id != pdev->cpu_port_nr)
{
SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
(dev_id, port_id, port_id - 1));
}
}
return SW_OK;
}
