static void ClkSet(sys_clk_t clock)
{
switch (clock)
{
case sysclk_XTAL16M:
if (!hw_cpm_check_xtal16m_status()) // XTAL16M disabled
{
hw_cpm_enable_xtal16m(); // Enable XTAL16M
}
hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M); // Set XTAL16 as sys_clk
hw_watchdog_unfreeze(); // Start watchdog
while (!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts
hw_qspi_set_div(HW_QSPI_DIV_1);
hw_watchdog_freeze(); // Stop watchdog
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
break;
case sysclk_PLL48:
if (hw_cpm_is_pll_locked() == 0)
{
hw_watchdog_unfreeze(); // Start watchdog
hw_cpm_pll_sys_on(); // Turn on PLL
hw_watchdog_freeze(); // Stop watchdog
}
hw_cpm_enable_pll_divider(); // Enable divider (div by 2)
hw_qspi_set_div(HW_QSPI_DIV_1);
hw_cpm_set_sysclk(SYS_CLK_IS_PLL);
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
break;
case sysclk_PLL96:
if (hw_cpm_is_pll_locked() == 0)
{
hw_watchdog_unfreeze(); // Start watchdog
hw_cpm_pll_sys_on(); // Turn on PLL
hw_watchdog_freeze(); // Stop watchdog
}
hw_cpm_disable_pll_divider(); // Disable divider (div by 1)
hw_qspi_set_div(HW_QSPI_DIV_2);
hw_cpm_set_sysclk(SYS_CLK_IS_PLL);
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
break;
default:
break;
}
}
/* carry out clock initialization sequence */
static void nortos_clk_setup(void)
{
// Setup DIVN
if (dg_configEXT_CRYSTAL_FREQ == EXT_CRYSTAL_IS_16M)
{
hw_cpm_set_divn(false); // External crystal is 16MHz
}
else
{
hw_cpm_set_divn(true); // External crystal is 32MHz
}
hw_cpm_enable_rc32k();
hw_cpm_lp_set_rc32k();
NVIC_ClearPendingIRQ(XTAL16RDY_IRQn);
nortos_xtal16m_settled = false;
NVIC_EnableIRQ(XTAL16RDY_IRQn); // Activate XTAL16 Ready IRQ
hw_cpm_set_xtal16m_settling_time(dg_configXTAL16_SETTLE_TIME_RC32K);
hw_cpm_enable_xtal16m(); // Enable XTAL16M
hw_watchdog_unfreeze(); // Start watchdog
while (!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts
/* Wait for XTAL16M to settle */
while (!nortos_xtal16m_settled);
hw_watchdog_freeze(); // Stop watchdog
hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M);
}
void ClkInit(void)
{
NVIC_ClearPendingIRQ(XTAL16RDY_IRQn);
NVIC_EnableIRQ(XTAL16RDY_IRQn); // Activate XTAL16 Ready IRQ
hw_cpm_set_divn(false); // External crystal is 16MHz
hw_cpm_enable_rc32k();
hw_cpm_lp_set_rc32k();
hw_cpm_set_xtal16m_settling_time(dg_configXTAL16_SETTLE_TIME_RC32K);
hw_cpm_enable_xtal16m(); // Enable XTAL16M
hw_cpm_configure_xtal32k_pins(); // Configure XTAL32K pins
hw_cpm_configure_xtal32k(); // Configure XTAL32K
hw_cpm_enable_xtal32k(); // Enable XTAL32K
hw_watchdog_unfreeze(); // Start watchdog
while (!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts
hw_watchdog_freeze(); // Stop watchdog
hw_cpm_set_recharge_period((uint16_t)dg_configSET_RECHARGE_PERIOD);
hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M);
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
hw_otpc_init();
hw_otpc_set_speed(HW_OTPC_SYS_CLK_FREQ_16);
}
__RETAINED_CODE void hw_watchdog_handle_int(unsigned long *exception_args)
{
// Reached this point due to a WDOG timeout
uint16_t pmu_ctrl_reg = CRG_TOP->PMU_CTRL_REG;
pmu_ctrl_reg |= ((1 << CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos) | /* turn off BLE */
(1 << CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos) | /* turn off FTDF */
(1 << CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos) | /* turn off radio PD */
(1 << CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos)); /* turn off peripheral power domain */
CRG_TOP->PMU_CTRL_REG = pmu_ctrl_reg;
REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, BLE_LP_RESET); /* reset the BLE LP timer */
#if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE)
hw_watchdog_freeze(); // Stop WDOG
ENABLE_DEBUGGER;
if (exception_args != NULL)
{
*(volatile unsigned long *)(STATUS_BASE) = exception_args[0]; // R0
*(volatile unsigned long *)(STATUS_BASE + 0x04) = exception_args[1]; // R1
*(volatile unsigned long *)(STATUS_BASE + 0x08) = exception_args[2]; // R2
*(volatile unsigned long *)(STATUS_BASE + 0x0C) = exception_args[3]; // R3
*(volatile unsigned long *)(STATUS_BASE + 0x10) = exception_args[4]; // R12
*(volatile unsigned long *)(STATUS_BASE + 0x14) = exception_args[5]; // LR
*(volatile unsigned long *)(STATUS_BASE + 0x18) = exception_args[6]; // PC
*(volatile unsigned long *)(STATUS_BASE + 0x1C) = exception_args[7]; // PSR
*(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)exception_args; // Stack Pointer
*(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR
*(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR
*(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR
*(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR
*(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR
*(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR
}
hw_cpm_assert_trigger_gpio();
if (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE))
{
__BKPT(0);
}
else
{
while (1);
}
#else // dg_configIMAGE_SETUP == DEVELOPMENT_MODE
if (exception_args != NULL)
{
nmi_event_data[0] = NMI_MAGIC_NUMBER;
nmi_event_data[1] = exception_args[0]; // R0
nmi_event_data[2] = exception_args[1]; // R1
nmi_event_data[3] = exception_args[2]; // R2
nmi_event_data[4] = exception_args[3]; // R3
nmi_event_data[5] = exception_args[4]; // R12
nmi_event_data[6] = exception_args[5]; // LR
nmi_event_data[7] = exception_args[6]; // PC
nmi_event_data[8] = exception_args[7]; // PSR
}
// Wait for the reset to occur
while (1);
#endif // dg_configIMAGE_SETUP == DEVELOPMENT_MODE
}
