void i2c_master_enable(i2c_dev *dev, uint32 flags) {
/* Bring the peripheral down for configuration */
i2c_peripheral_disable(dev);
/* Reset the bus when requested so */
if (flags & I2C_BUS_RESET)
i2c_bus_reset(dev);
/* Turn on the clock and set GPIO modes */
i2c_init(dev);
i2c_config_gpios(dev);
/* Configure analog and digital filters */
/* TODO ANFOFF, DNF */
/* Configure the clock and rise time */
dev->regs->TIMINGR = I2C_TIMING_10_kHz;
/* Configure NOSTRETCH behaviour */
/* TODO NOSTRETCH */
/* Enable all interrupts */ /* FIXME not yet used on F3 */
//nvic_irq_enable(dev->ev_nvic_line);
//nvic_irq_enable(dev->er_nvic_line);
//i2c_enable_irq(dev, 0xFE); /* All interrupts */
/* Make it go! */
i2c_peripheral_enable(dev);
dev->state = I2C_STATE_IDLE;
}
/**
* @brief Initialize an I2C device as bus master
* @param dev Device to enable
* @param flags Bitwise or of the following I2C options:
* I2C_FAST_MODE: 400 khz operation,
* I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
* fast mode),
* I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
* initialization,
* I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
* I2C_REMAP: (deprecated, STM32F1 only) Remap I2C1 to SCL/PB8
* SDA/PB9.
*/
void i2c_master_enable(i2c_dev *dev, uint32 flags) {
/* Reset the bus. Clock out any hung slaves. */
if (flags & I2C_BUS_RESET) {
fooprint("i2c_master_enable: calling i2c_bus_reset");
i2c_bus_reset(dev);
}
fooprint("i2c_master_enable: entry");
/* PE must be disabled to configure the device */
// ASSERT(!(dev->regs->CR1 & I2C_CR1_PE));
/* Ugh */
//_i2c_handle_remap(dev, flags);
fooprint("i2c_master_enable: calling i2c_init");
/* Turn on clock and set GPIO modes */
i2c_init(dev);
fooprint("i2c_master_enable: calling i2c_config_gpios");
i2c_config_gpios(dev);
fooprint("i2c_master_enable: calling set_freq_scl");
/* Configure clock and rise time */
set_freq_scl(dev, flags);
fooprint("i2c_master_enable: calling nvic_irq_enable(ev)");
/* Enable event and buffer interrupts */
nvic_irq_enable(dev->ev_nvic_line);
fooprint("i2c_master_enable: calling nvic_irq_enable(er)");
nvic_irq_enable(dev->er_nvic_line);
//gutted
fooprint("i2c_master_enable: calling i2c_enable_irq");
i2c_enable_irq(dev, I2C_CFGR_STOIEN_MASK | I2C_CFGR_ACKIEN_MASK | I2C_CFGR_RXIEN_MASK | I2C_CFGR_TXIEN_MASK | I2C_CFGR_STAIEN_MASK | I2C_CFGR_ARBLIEN_MASK);
/* Make it go! */
fooprint("i2c_master_enable: calling i2c_peripheral_enable");
//gutted
i2c_peripheral_enable(dev);
dev->state = I2C_STATE_IDLE;
fooprint("i2c_master_enable: exit, dev-state = I2C_STATE_IDLE");
}
/**
* @brief Initialize an I2C device as bus master
* @param dev Device to enable
* @param flags Bitwise or of the following I2C options:
* I2C_FAST_MODE: 400 khz operation,
* I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
* fast mode),
* I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
* initialization,
* I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
* I2C_REMAP: (deprecated, STM32F1 only) Remap I2C1 to SCL/PB8
* SDA/PB9.
*/
void i2c_master_enable(i2c_dev *dev, uint32 flags) {
/* PE must be disabled to configure the device */
ASSERT(!(dev->regs->CR1 & I2C_CR1_PE));
/* Ugh */
_i2c_handle_remap(dev, flags);
/* Reset the bus. Clock out any hung slaves. */
if (flags & I2C_BUS_RESET) {
i2c_bus_reset(dev);
}
/* Turn on clock and set GPIO modes */
i2c_init(dev);
i2c_config_gpios(dev);
/* Configure clock and rise time */
set_ccr_trise(dev, flags);
/* Enable event and buffer interrupts */
nvic_irq_enable(dev->ev_nvic_line);
nvic_irq_enable(dev->er_nvic_line);
i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR);
/* Configure the slave unit */
if (flags & I2C_SLAVE_DUAL_ADDRESS) {
i2c_slave_dual_address_enable(dev);
}
if (flags & I2C_SLAVE_GENERAL_CALL) {
i2c_slave_general_call_enable(dev);
}
/* store all of the flags */
dev->config_flags = flags;
/* Make it go! */
i2c_peripheral_enable(dev);
i2c_enable_ack(dev);
dev->state = I2C_STATE_IDLE;
}
/**
* @brief Initialize an I2C device as bus master
* @param dev Device to enable
* @param flags Bitwise or of the following I2C options:
* I2C_FAST_MODE: 400 khz operation,
* I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
* fast mode),
* I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
* initialization,
* I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
* I2C_REMAP: Remap I2C1 to SCL/PB8 SDA/PB9.
*/
void i2c_master_enable(i2c_dev *dev, uint32 flags) {
#define I2C_CLK (STM32_PCLK1/1000000)
uint32 ccr = 0;
uint32 trise = 0;
/* PE must be disabled to configure the device */
ASSERT(!(dev->regs->CR1 & I2C_CR1_PE));
if ((dev == I2C1) && (flags & I2C_REMAP)) {
afio_remap(AFIO_REMAP_I2C1);
I2C1->sda_pin = 9;
I2C1->scl_pin = 8;
}
/* Reset the bus. Clock out any hung slaves. */
if (flags & I2C_BUS_RESET) {
i2c_bus_reset(dev);
}
/* Turn on clock and set GPIO modes */
i2c_init(dev);
gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_AF_OUTPUT_OD);
gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_AF_OUTPUT_OD);
/* I2C1 and I2C2 are fed from APB1, clocked at 36MHz */
i2c_set_input_clk(dev, I2C_CLK);
if (flags & I2C_FAST_MODE) {
ccr |= I2C_CCR_FS;
if (flags & I2C_DUTY_16_9) {
/* Tlow/Thigh = 16/9 */
ccr |= I2C_CCR_DUTY;
ccr |= STM32_PCLK1/(400000 * 25);
} else {
/* Tlow/Thigh = 2 */
ccr |= STM32_PCLK1/(400000 * 3);
}
trise = (300 * (I2C_CLK)/1000) + 1;
} else {
/* Tlow/Thigh = 1 */
ccr = STM32_PCLK1/(100000 * 2);
trise = I2C_CLK + 1;
}
/* Set minimum required value if CCR < 1*/
if ((ccr & I2C_CCR_CCR) == 0) {
ccr |= 0x1;
}
i2c_set_clk_control(dev, ccr);
i2c_set_trise(dev, trise);
/* Enable event and buffer interrupts */
nvic_irq_enable(dev->ev_nvic_line);
nvic_irq_enable(dev->er_nvic_line);
i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR);
/*
* Important STM32 Errata:
*
* See STM32F10xx8 and STM32F10xxB Errata sheet (Doc ID 14574 Rev 8),
* Section 2.11.1, 2.11.2.
*
* 2.11.1:
* When the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events are not
* managed before the current byte is being transferred, problems may be
* encountered such as receiving an extra byte, reading the same data twice
* or missing data.
*
* 2.11.2:
* In Master Receiver mode, when closing the communication using
* method 2, the content of the last read data can be corrupted.
*
* If the user software is not able to read the data N-1 before the STOP
* condition is generated on the bus, the content of the shift register
* (data N) will be corrupted. (data N is shifted 1-bit to the left).
*
* ----------------------------------------------------------------------
*
* In order to ensure that events are not missed, the i2c interrupt must
* not be preempted. We set the i2c interrupt priority to be the highest
* interrupt in the system (priority level 0). All other interrupts have
* been initialized to priority level 16. See nvic_init().
*/
nvic_irq_set_priority(dev->ev_nvic_line, 0);
nvic_irq_set_priority(dev->er_nvic_line, 0);
/* Make it go! */
i2c_peripheral_enable(dev);
dev->state = I2C_STATE_IDLE;
}
