static int i2s_configure(struct tegra_i2s_info *info ) { struct platform_device *pdev = info->pdev; struct tegra_audio_platform_data *pdata = pdev->dev.platform_data; unsigned int i2s_id = pdev->id; unsigned int rate; i2s_enable_fifos(i2s_id, 0); i2s_fifo_clear(i2s_id, I2S_FIFO_TX); i2s_fifo_clear(i2s_id, I2S_FIFO_RX); i2s_set_left_right_control_polarity(i2s_id, 0); /* default */ rate = clk_get_rate(info->i2s_clk); if (info->bit_format == TEGRA_AUDIO_BIT_FORMAT_DSP) rate *= 2; i2s_set_master(i2s_id, pdata->i2s_master); info->i2s_master = pdata->i2s_master; if (pdata->i2s_master && pdata->i2s_master_clk) i2s_set_channel_bit_count(i2s_id, pdata->i2s_master_clk, rate); i2s_set_fifo_mode(i2s_id, I2S_FIFO_TX, 1); i2s_set_fifo_mode(i2s_id, I2S_FIFO_RX, 0); i2s_set_bit_format(i2s_id, pdata->mode); i2s_set_bit_size(i2s_id, pdata->bit_size); i2s_set_fifo_format(i2s_id, pdata->fifo_fmt); if (i2s_id == 0) en_dmic = pdata->en_dmic; return 0; }
static int tegra_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) { struct tegra_i2s_info *info = cpu_dai->private_data; unsigned int i2s_id = cpu_dai->id; int val1, val2; switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: val1 = 1; break; case SND_SOC_DAIFMT_CBM_CFM: val1 = 0; break; case SND_SOC_DAIFMT_CBS_CFM: case SND_SOC_DAIFMT_CBM_CFS: /* Tegra does not support different combinations of * master and slave for FSYNC and BCLK */ default: return -EINVAL; } i2s_set_master(i2s_id, val1); info->i2s_master = val1; switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_DSP_A: val1 = I2S_BIT_FORMAT_DSP; val2 = 0; break; case SND_SOC_DAIFMT_DSP_B: val1 = I2S_BIT_FORMAT_DSP; val2 = 1; break; case SND_SOC_DAIFMT_I2S: val1 = I2S_BIT_FORMAT_I2S; val2 = 0; break; case SND_SOC_DAIFMT_RIGHT_J: val1 = I2S_BIT_FORMAT_RJM; val2 = 0; break; case SND_SOC_DAIFMT_LEFT_J: val1 = I2S_BIT_FORMAT_LJM; val2 = 0; break; default: return -EINVAL; } i2s_set_bit_format(i2s_id, val1); i2s_set_left_right_control_polarity(i2s_id, val2); return 0; }
int am_set_device_format(aud_dev_info* devinfo, am_dev_format_info *format) { if (devinfo->dev_type == AUDIO_I2S_DEVICE) { i2s_set_loopback(devinfo->dev_id, format->loopmode); i2s_set_master(devinfo->dev_id, format->mastermode); i2s_set_bit_format(devinfo->dev_id, format->audiomode); i2s_set_left_right_control_polarity( devinfo->dev_id, format->polarity); } else if (devinfo->dev_type == AUDIO_SPDIF_DEVICE) { } return 0; }
static int i2s_configure(struct tegra_i2s_info *info ) { struct platform_device *pdev = info->pdev; struct tegra_audio_platform_data *pdata = pdev->dev.platform_data; struct clk *i2s_clk; unsigned int i2s_id = pdev->id; unsigned int rate; i2s_enable_fifos(i2s_id, 0); i2s_fifo_clear(i2s_id, I2S_FIFO_TX); i2s_fifo_clear(i2s_id, I2S_FIFO_RX); i2s_set_left_right_control_polarity(i2s_id, 0); /* default */ i2s_clk = clk_get(&pdev->dev, NULL); if (!i2s_clk) { dev_err(&pdev->dev, "%s: could not get i2s clock\n", __func__); return -EIO; } rate = clk_get_rate(i2s_clk); if (info->bit_format == TEGRA_AUDIO_BIT_FORMAT_DSP) rate *= 2; if (pdata->i2s_master && pdata->i2s_master_clk) i2s_set_channel_bit_count(i2s_id, pdata->i2s_master_clk, rate); i2s_set_master(i2s_id, pdata->i2s_master); i2s_set_fifo_mode(i2s_id, I2S_FIFO_TX, 1); i2s_set_fifo_mode(i2s_id, I2S_FIFO_RX, 0); i2s_set_bit_format(i2s_id, pdata->mode); i2s_set_bit_size(i2s_id, pdata->bit_size); i2s_set_fifo_format(i2s_id, pdata->fifo_fmt); return 0; }