void arch_post_mm_init(void)
{
if (config.cpu_active == 1) {
/* Initialize IRQ routing */
irq_init(IRQ_COUNT, IRQ_COUNT);
/* hard clock */
i8254_init();
#if (defined(CONFIG_FB) || defined(CONFIG_EGA))
bool bfb = false;
#endif
#ifdef CONFIG_FB
bfb = bfb_init();
#endif
#ifdef CONFIG_EGA
if (!bfb) {
outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
if (egadev)
stdout_wire(egadev);
}
#endif
/* Merge all memory zones to 1 big zone */
zone_merge_all();
}
}
void __init adi_chips_init(void)
{
printk(MOD_NAME "Initializing chip drivers\n");
i8259a_init();
i8254_init();
rtc_init();
intel_init(0);
}
void
init_x86(const char *karg)
{
enum {
code = GATE_PRESENT | GATE_TYPE_RX,
ucode = code | GATE_DPL3,
data = GATE_PRESENT | GATE_TYPE_RW,
udata = data | GATE_DPL3,
attr = GATE_PAGEGRAN | GATE_OP32,
tss0 = GATE_PRESENT | GATE_TYPE_TASK,
intrpt_attr = GATE_PRESENT | GATE_TYPE_INTRPT,
trap_attr = GATE_PRESENT | GATE_TYPE_TRAP
};
int i = 0;
__kernarg = karg;
if (1)
for (i = 0; i < 255 && *karg; karg++, i++) {
kernarg[i] = *karg;
}
kernarg[i] = 0;
kargs_init();
// Ustawienie GDT
mem_zero(&p_gdt, sizeof(p_gdt));
mem_zero(&p_tss0, sizeof(p_tss0));
setgdt(SEL_CODE, 0x0, 0xfffff, code, attr);
setgdt(SEL_DATA, 0x0, 0xfffff, data, attr);
setgdt(SEL_UCODE, 0x0, 0xfffff, ucode, attr);
setgdt(SEL_UDATA, 0x0, 0xfffff, udata, attr);
setgdt(SEL_TSS0, (uintptr_t)&p_tss0, sizeof(p_tss0), tss0, 0);
p_tss0.tss_io = 0;
p_tss0.tss_ss0 = 0x10;
// p_tss0.tss_cs=0x8;
// p_tss0.tss_ds=p_tss0.tss_es=p_tss0.tss_fs=p_tss0.tss_gs=0x10;
mem_zero(&p_gdtr, sizeof(p_gdtr));
p_gdtr.base = &p_gdt;
p_gdtr.limit = sizeof(p_gdt) -1;
cpu_gdt_load(&p_gdtr);
cpu_tr_load(SEL_MK(SEL_TSS0, SEL_DPL3));
extern void megaloop(void);
// Ustawienie IDT
for (i = 0; i < 0x100; i++) {
setidt(i, SEL_MK(SEL_CODE, SEL_DPL0), (uintptr_t)_unhnd_intrpt,
intrpt_attr);
}
for (i = 0; i < 0x20; i++) {
setidt(i, SEL_MK(SEL_CODE, SEL_DPL0), (uintptr_t)trap_table[i], trap_attr);
}
for (i = 0; i <= 23; i++) {
setidt(i+0x20, SEL_MK(SEL_CODE, SEL_DPL0), irq_table[i], intrpt_attr);
}
setidt(INTRPT_SYSCALL, SEL_MK(SEL_CODE, SEL_DPL0),
(uintptr_t)_intrpt_syscall, intrpt_attr | GATE_DPL3);
mem_zero(&p_idtr, sizeof(p_idtr));
p_idtr.base = &p_idt;
p_idtr.limit = sizeof(p_idt)-1;
cpu_idt_load(&p_idtr);
i8259a_init();
i8254_init();
pckbd_init();
vm_low_init();
video_init();
bus_isa_init();
bus_pci_init();
irq_enable();
_cpu_info();
}