Exemple #1
0
/* via ide func */
static int vt82c686b_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);;
    uint8_t *pci_conf = d->dev.config;

    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_IDE);
    pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
    pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
    pci_config_set_revision(pci_conf,0x06); /* Revision 0.6 */
    pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);

    qemu_register_reset(via_reset, d);
    pci_register_bar((PCIDevice *)d, 4, 0x10,
                           PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);

    vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);

    ide_bus_new(&d->bus[0], &d->dev.qdev);
    ide_bus_new(&d->bus[1], &d->dev.qdev);
    ide_init2(&d->bus[0], isa_reserve_irq(14));
    ide_init2(&d->bus[1], isa_reserve_irq(15));
    ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
    ide_init_ioport(&d->bus[1], 0x170, 0x376);

    return 0;
}
Exemple #2
0
static int pc98_ide_initfn(ISADevice *dev)
{
    PC98IDEState *s = DO_UPCAST(PC98IDEState, dev, dev);
    int i;

    ide_bus_new(&s->bus[0], &s->dev.qdev, 0);
    ide_bus_new(&s->bus[1], &s->dev.qdev, 1);

    isa_init_irq(dev, &s->irq, s->isairq);
    ide_init2(&s->bus[0], s->irq);
    ide_init2(&s->bus[1], s->irq);

    register_ioport_write(0xf0, 1, 1, pc98_ide_cpu_shutdown, s);
    register_ioport_read(0xf0, 1, 1, pc98_ide_connection_read, s);
    isa_init_ioport(dev, 0xf0);
    register_ioport_write(0x430, 1, 1, pc98_ide_bank_write, s);
    register_ioport_read(0x430, 1, 1, pc98_ide_bank_read, s);
    isa_init_ioport(dev, 0x430);
    register_ioport_write(0x432, 1, 1, pc98_ide_bank_write, s);
    register_ioport_read(0x432, 1, 1, pc98_ide_bank_read, s);
    isa_init_ioport(dev, 0x432);
    for (i = 0; i < 8; i++) {
        register_ioport_write(0x640 + (i << 1), 1, 1, pc98_ide_ioport_write, s);
        register_ioport_read(0x640 + (i << 1), 1, 1, pc98_ide_ioport_read, s);
        isa_init_ioport(dev, 0x640 + (i << 1));
    }
    register_ioport_write(0x640, 2, 2, pc98_ide_data_writew, s);
    register_ioport_read(0x640, 2, 2, pc98_ide_data_readw, s);
    /*isa_init_ioport_range(dev, 0x640, 2);*/
    register_ioport_write(0x640, 4, 4, pc98_ide_data_writel, s);
    register_ioport_read(0x640, 4, 4, pc98_ide_data_readl, s);
    /*isa_init_ioport_range(dev, 0x640, 4);*/
    register_ioport_write(0x74c, 1, 1, pc98_ide_digital_write, s);
    register_ioport_read(0x74c, 1, 1, pc98_ide_status_read, s);
    isa_init_ioport(dev, 0x74c);
    register_ioport_read(0x74e, 1, 1, pc98_ide_digital_read, s);
    isa_init_ioport(dev, 0x74e);

    vmstate_register(&dev->qdev, 0, &vmstate_ide_pc98, s);
    pc98_ide_reset(&dev->qdev);

    return 0;
};
Exemple #3
0
static void mmio_ide_realizefn(DeviceState *dev, Error **errp)
{
    SysBusDevice *d = SYS_BUS_DEVICE(dev);
    MMIOState *s = MMIO_IDE(dev);

    ide_init2(&s->bus, s->irq);

    memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s,
                          "ide-mmio.1", 16 << s->shift);
    memory_region_init_io(&s->iomem2, OBJECT(s), &mmio_ide_cs_ops, s,
                          "ide-mmio.2", 2 << s->shift);
    sysbus_init_mmio(d, &s->iomem1);
    sysbus_init_mmio(d, &s->iomem2);
}
Exemple #4
0
/* CMD646 PCI IDE controller */
static int pci_cmd646_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    uint8_t *pci_conf = d->dev.config;
    qemu_irq *irq;
    int i;

    pci_conf[PCI_CLASS_PROG] = 0x8f;

    pci_conf[0x51] = 0x04; // enable IDE0
    if (d->secondary) {
        /* XXX: if not enabled, really disable the seconday IDE controller */
        pci_conf[0x51] |= 0x08; /* enable IDE1 */
    }

    setup_cmd646_bar(d, 0);
    setup_cmd646_bar(d, 1);
    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
    pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
    pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    /* TODO: RST# value should be 0 */
    pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1

    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], &d->dev.qdev, i);
        ide_init2(&d->bus[i], irq[i]);

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
                                         &d->bmdma[i].dma);
    }

    vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
    qemu_register_reset(cmd646_reset, d);
    return 0;
}
Exemple #5
0
static void via_ide_realize(PCIDevice *dev, Error **errp)
{
    PCIIDEState *d = PCI_IDE(dev);
    uint8_t *pci_conf = dev->config;
    int i;

    pci_config_set_prog_interface(pci_conf, 0x8f); /* native PCI ATA mode */
    pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
    dev->wmask[PCI_INTERRUPT_LINE] = 0xf;

    qemu_register_reset(via_ide_reset, d);

    memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
                          &d->bus[0], "via-ide0-data", 8);
    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);

    memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
                          &d->bus[0], "via-ide0-cmd", 4);
    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);

    memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
                          &d->bus[1], "via-ide1-data", 8);
    pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);

    memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
                          &d->bus[1], "via-ide1-cmd", 4);
    pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);

    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);

    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
        ide_init2(&d->bus[i], qemu_allocate_irq(via_ide_set_irq, d, i));

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        ide_register_restart_cb(&d->bus[i]);
    }
}
Exemple #6
0
static void vt82c686b_init_ports(PCIIDEState *d) {
    static const struct {
        int iobase;
        int iobase2;
        int isairq;
    } port_info[] = {
        {0x1f0, 0x3f6, 14},
        {0x170, 0x376, 15},
    };
    int i;

    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
        ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
                        port_info[i].iobase2);
        ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        ide_register_restart_cb(&d->bus[i]);
    }
}
static void pci_piix_init_ports(PCIIDEState *d) {
    int i;
    struct {
        int iobase;
        int iobase2;
        int isairq;
    } port_info[] = {
        {0x1f0, 0x3f6, 14},
        {0x170, 0x376, 15},
    };

    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], &d->dev.qdev, i);
        ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
        ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));

        bmdma_init(&d->bus[i], &d->bmdma[i]);
        d->bmdma[i].bus = &d->bus[i];
        qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
                                         &d->bmdma[i].dma);
    }
}
Exemple #8
0
static void vt82c686b_init_ports(PCIIDEState *d) {
    static const struct {
        int iobase;
        int iobase2;
        int isairq;
    } port_info[] = {
        {0x1f0, 0x3f6, 14},
        {0x170, 0x376, 15},
    };
    int i;

    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], DEVICE(d), i, 2);
        ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
                        port_info[i].iobase2);
        ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
                                         &d->bmdma[i].dma);
    }
}