static int pcm043_devices_init(void)
{
uint32_t reg;
char *envstr;
unsigned long bbu_nand_flags = 0;
/* CS0: Nor Flash */
imx35_setup_weimcs(5, 0x22C0CF00, 0x75000D01, 0x00000900);
led_gpio_register(&led0);
reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
else
nand_info.width = 1; /* 8 bit */
imx35_add_fec(&fec_info);
/*
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
switch (bootsource_get()) {
case BOOTSOURCE_NAND:
devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
envstr = "NAND";
bbu_nand_flags = BBU_HANDLER_FLAG_DEFAULT;
break;
case BOOTSOURCE_NOR:
default:
devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); /* ourself */
devfs_add_partition("nor0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env0"); /* environment */
protect_file("/dev/env0", 1);
envstr = "NOR";
break;
}
pr_info("using environment from %s flash\n", envstr);
imx35_add_fb(&ipu_fb_data);
armlinux_set_architecture(MACH_TYPE_PCM043);
imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox",
bbu_nand_flags);
return 0;
}
static int f3s_devices_init(void)
{
uint32_t reg;
/* CS0: Nor Flash */
imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
else
nand_info.width = 1; /* 8 bit */
/*
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0);
switch ((reg >> 25) & 0x3) {
case 0x01: /* NAND is the source */
devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
break;
case 0x00: /* NOR is the source */
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
break;
}
set_silicon_rev(imx_silicon_revision());
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx35_add_i2c0(NULL);
imx35_add_fec(&fec_info);
add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX35_CS5_BASE_ADDR, MX35_CS5_SIZE,
IORESOURCE_MEM, NULL);
imx35_add_mmc0(NULL);
imx35_add_fb(&ipu_fb_data);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_MX35_3DS);
return 0;
}
static int cupid_core_setup(void)
{
u32 tmp;
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, MX35_AIPS1_BASE_ADDR);
writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
writel(0x77777777, MX35_AIPS2_BASE_ADDR);
writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50);
tmp &= 0x00FFFFFF;
writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50);
writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50);
tmp &= 0x00FFFFFF;
writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50);
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
#define MAX_PARAM1 0x00302154
writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */
writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
/* SGPCR - always park on last master */
writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */
writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */
writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */
writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */
writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */
/* MGPCR - restore default values */
writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */
writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */
writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */
writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */
writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */
writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */
/* CS0: NOR Flash */
imx35_setup_weimcs(0, 0x0000DCF6, 0x444A4541, 0x44443302);
/*
* M3IF Control Register (M3IFCTL)
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
* MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000
* MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000
* MRRP[3] = USB not on priority list (0 << 0) = 0x00000000
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
* MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
* ------------
* 0x00000040
*/
writel(0x40, MX35_M3IF_BASE_ADDR);
return 0;
}
static int f3s_core_init(void)
{
u32 reg;
/* CS5: smc9117 */
imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00);
/* enable clock for I2C1 and FEC */
reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, MX35_AIPS1_BASE_ADDR);
writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
writel(0x77777777, MX35_AIPS2_BASE_ADDR);
writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
reg = readl(MX35_AIPS1_BASE_ADDR + 0x50);
reg &= 0x00FFFFFF;
writel(reg, MX35_AIPS1_BASE_ADDR + 0x50);
writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
reg = readl(MX35_AIPS2_BASE_ADDR + 0x50);
reg &= 0x00FFFFFF;
writel(reg, MX35_AIPS2_BASE_ADDR + 0x50);
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
#define MAX_PARAM1 0x00302154
writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */
writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
/* SGPCR - always park on last master */
writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */
writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */
writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */
writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */
writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */
/* MGPCR - restore default values */
writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */
writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */
writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */
writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */
writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */
writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */
return 0;
}
