ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
arm_setup_stack(0xf8020000 - 8);
imx53_init_lowlevel_early(800);
fdt = (uint32_t)__dtb_imx53_mba53_start - get_runtime_offset();
start_imx53_tqma53_common(fdt);
}
void __naked barebox_arm_reset_vector(void)
{
imx5_cpu_lowlevel_init();
arm_setup_stack(0xf8020000 - 8);
/*
* For the TX53 rev 8030 the SDRAM setup is not stable without
* the proper PLL setup. It will crash once we enable the MMU,
* so do the PLL setup here.
*/
if (IS_ENABLED(CONFIG_TX53_REV_XX30))
imx53_init_lowlevel_early(800);
imx53_barebox_entry(NULL);
}
ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2)
{
void *fdt;
imx5_cpu_lowlevel_init();
arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
IMD_USED(tqma53_memsize_1G);
imx53_init_lowlevel_early(800);
fdt = __dtb_imx53_mba53_start + get_runtime_offset();
start_imx53_tqma53_common(fdt);
}
ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2)
{
void *fdt;
arm_cpu_lowlevel_init();
arm_setup_stack(0xf8020000 - 8);
IMD_USED(tqma53_memsize_1G);
imx53_init_lowlevel_early(800);
fdt = __dtb_imx53_mba53_start - get_runtime_offset();
start_imx53_tqma53_common(fdt);
}
static noinline void imx53_guf_vincell_init(int is_lt)
{
void __iomem *ccm = (void *)MX53_CCM_BASE_ADDR;
void __iomem *uart = IOMEM(MX53_UART2_BASE_ADDR);
void *fdt;
u32 r;
enum bootsource src;
int instance;
arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
writel(0x0088494c, ccm + MX5_CCM_CBCDR);
writel(0x02b12f0a, ccm + MX5_CCM_CSCMR2);
imx53_ungate_all_peripherals();
imx53_init_lowlevel_early(800);
writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c);
writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278);
imx53_uart_setup(uart);
pbl_set_putc(imx_uart_putc, uart);
pr_debug("GuF Vincell\n");
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (!(r > 0x70000000 && r < 0xf0000000)) {
disable_watchdog();
configure_dram_iomux();
imx_esdctlv4_init();
imx53_get_boot_source(&src, &instance);
if (src == BOOTSOURCE_NAND &&
IS_ENABLED(CONFIG_MACH_GUF_VINCELL_XLOAD))
imx53_nand_start_image();
}
if (is_lt)
fdt = __dtb_imx53_guf_vincell_lt_start;
else
fdt = __dtb_imx53_guf_vincell_start;
imx53_barebox_entry(fdt);
}
void imx53_init_lowlevel(unsigned int cpufreq_mhz)
{
imx53_init_lowlevel_early(cpufreq_mhz);
clock_notifier_call_chain();
}
void __naked barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
imx53_init_lowlevel_early(800);
imx53_barebox_entry(0);
}
