static void __imx53_guf_vincell_init(int is_lt) { arm_early_mmu_cache_invalidate(); imx5_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); barrier(); imx53_guf_vincell_init(is_lt); }
ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2) { void *fdt; imx5_cpu_lowlevel_init(); fdt = __dtb_imx51_babbage_start - get_runtime_offset(); imx51_barebox_entry(fdt); }
ENTRY_FUNCTION(start_imx53_vmx53, r0, r1, r2) { void *fdt; imx5_cpu_lowlevel_init(); arm_setup_stack(0xf8020000 - 8); fdt = __dtb_imx53_voipac_bsb_start - get_runtime_offset(); imx53_barebox_entry(fdt); }
ENTRY_FUNCTION(start_ccxmx51, r0, r1, r2) { extern char __dtb_imx51_ccxmx51_start[]; void *fdt; imx5_cpu_lowlevel_init(); arm_setup_stack(0x20000000 - 16); fdt = __dtb_imx51_ccxmx51_start + get_runtime_offset(); barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, fdt); }
void __naked barebox_arm_reset_vector(void) { imx5_cpu_lowlevel_init(); arm_setup_stack(0xf8020000 - 8); /* * For the TX53 rev 8030 the SDRAM setup is not stable without * the proper PLL setup. It will crash once we enable the MMU, * so do the PLL setup here. */ if (IS_ENABLED(CONFIG_TX53_REV_XX30)) imx53_init_lowlevel_early(800); imx53_barebox_entry(NULL); }
ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2) { void *fdt; imx5_cpu_lowlevel_init(); arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); IMD_USED(tqma53_memsize_1G); imx53_init_lowlevel_early(800); fdt = __dtb_imx53_mba53_start + get_runtime_offset(); start_imx53_tqma53_common(fdt); }
void __naked barebox_arm_reset_vector(void) { imx5_cpu_lowlevel_init(); arm_setup_stack(0xf8020000 - 8); imx53_barebox_entry(NULL); }