static int imx_pcm_probe(struct platform_device *pdev) { if (strcmp(pdev->id_entry->name, "imx-fiq-pcm-audio") == 0) return imx_pcm_fiq_init(pdev); return imx_pcm_dma_init(pdev); }
static int fsl_esai_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct fsl_esai *esai_priv; struct resource *res; const uint32_t *iprop; void __iomem *regs; int irq, ret; esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL); if (!esai_priv) return -ENOMEM; esai_priv->pdev = pdev; strcpy(esai_priv->name, np->name); /* Get the addresses and IRQ */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(regs)) return PTR_ERR(regs); esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "core", regs, &fsl_esai_regmap_config); if (IS_ERR(esai_priv->regmap)) { dev_err(&pdev->dev, "failed to init regmap: %ld\n", PTR_ERR(esai_priv->regmap)); return PTR_ERR(esai_priv->regmap); } esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); if (IS_ERR(esai_priv->coreclk)) { dev_err(&pdev->dev, "failed to get core clock: %ld\n", PTR_ERR(esai_priv->coreclk)); return PTR_ERR(esai_priv->coreclk); } esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal"); if (IS_ERR(esai_priv->extalclk)) dev_warn(&pdev->dev, "failed to get extal clock: %ld\n", PTR_ERR(esai_priv->extalclk)); esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys"); if (IS_ERR(esai_priv->fsysclk)) dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n", PTR_ERR(esai_priv->fsysclk)); irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); return irq; } ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0, esai_priv->name, esai_priv); if (ret) { dev_err(&pdev->dev, "failed to claim irq %u\n", irq); return ret; } /* Set a default slot size */ esai_priv->slot_width = 32; /* Set a default master/slave state */ esai_priv->slave_mode = true; /* Determine the FIFO depth */ iprop = of_get_property(np, "fsl,fifo-depth", NULL); if (iprop) esai_priv->fifo_depth = be32_to_cpup(iprop); else esai_priv->fifo_depth = 64; esai_priv->dma_params_tx.maxburst = 16; esai_priv->dma_params_rx.maxburst = 16; esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR; esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR; esai_priv->synchronous = of_property_read_bool(np, "fsl,esai-synchronous"); /* Implement full symmetry for synchronous mode */ if (esai_priv->synchronous) { fsl_esai_dai.symmetric_rates = 1; fsl_esai_dai.symmetric_channels = 1; fsl_esai_dai.symmetric_samplebits = 1; } dev_set_drvdata(&pdev->dev, esai_priv); /* Reset ESAI unit */ ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST); if (ret) { dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret); return ret; } /* * We need to enable ESAI so as to access some of its registers. * Otherwise, we would fail to dump regmap from user space. */ ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN); if (ret) { dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret); return ret; } ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component, &fsl_esai_dai, 1); if (ret) { dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); return ret; } ret = imx_pcm_dma_init(pdev); if (ret) dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret); return ret; }