static int imx_startup(struct uart_port *port) { struct imx_port *sport = (struct imx_port *)port; int retval; unsigned long flags, temp; imx_setup_ufcr(sport, 0); /* disable the DREN bit (Data Ready interrupt enable) before * requesting IRQs */ temp = readl(sport->port.membase + UCR4); writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); /* * Allocate the IRQ */ retval = request_irq(sport->rxirq, imx_rxint, 0, DRIVER_NAME, sport); if (retval) goto error_out1; retval = request_irq(sport->txirq, imx_txint, 0, DRIVER_NAME, sport); if (retval) goto error_out2; retval = request_irq(sport->rtsirq, imx_rtsint, (sport->rtsirq < IMX_IRQS) ? 0 : IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, DRIVER_NAME, sport); if (retval) goto error_out3; /* * Finally, clear and enable interrupts */ writel(USR1_RTSD, sport->port.membase + USR1); temp = readl(sport->port.membase + UCR1); temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; writel(temp, sport->port.membase + UCR1); temp = readl(sport->port.membase + UCR2); temp |= (UCR2_RXEN | UCR2_TXEN); writel(temp, sport->port.membase + UCR2); /* * Enable modem status interrupts */ spin_lock_irqsave(&sport->port.lock,flags); imx_enable_ms(&sport->port); spin_unlock_irqrestore(&sport->port.lock,flags); return 0; error_out3: free_irq(sport->txirq, sport); error_out2: free_irq(sport->rxirq, sport); error_out1: return retval; }
static int imx_startup(struct uart_port *port) { struct imx_port *sport = (struct imx_port *)port; int retval; unsigned long flags; imx_setup_ufcr(sport, 0); /* disable the DREN bit (Data Ready interrupt enable) before * requesting IRQs */ UCR4((u32)sport->port.membase) &= ~UCR4_DREN; /* * Allocate the IRQ */ retval = request_irq(sport->rxirq, imx_rxint, 0, DRIVER_NAME, sport); if (retval) goto error_out1; retval = request_irq(sport->txirq, imx_txint, 0, DRIVER_NAME, sport); if (retval) goto error_out2; retval = request_irq(sport->rtsirq, imx_rtsint, IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, DRIVER_NAME, sport); if (retval) goto error_out3; /* * Finally, clear and enable interrupts */ USR1((u32)sport->port.membase) = USR1_RTSD; UCR1((u32)sport->port.membase) |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); UCR2((u32)sport->port.membase) |= (UCR2_RXEN | UCR2_TXEN); /* * Enable modem status interrupts */ spin_lock_irqsave(&sport->port.lock,flags); imx_enable_ms(&sport->port); spin_unlock_irqrestore(&sport->port.lock,flags); return 0; error_out3: free_irq(sport->txirq, sport); error_out2: free_irq(sport->rxirq, sport); error_out1: return retval; }
static int imx_startup(struct uart_port *port) { struct imx_port *sport = (struct imx_port *)port; int retval; unsigned long flags, temp; imx_setup_ufcr(sport, 0); /* disable the DREN bit (Data Ready interrupt enable) before * requesting IRQs */ temp = readl(sport->port.membase + UCR4); if (USE_IRDA(sport)) temp |= UCR4_IRSC; /* set the trigger level for CTS */ temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF); temp |= CTSTL<< UCR4_CTSTL_SHF; writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); if (USE_IRDA(sport)) { /* reset fifo's and state machines */ int i = 100; temp = readl(sport->port.membase + UCR2); temp &= ~UCR2_SRST; writel(temp, sport->port.membase + UCR2); while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) { udelay(1); } } /* * Allocate the IRQ(s) i.MX1 has three interrupts whereas later * chips only have one interrupt. */ if (sport->txirq > 0) { retval = request_irq(sport->rxirq, imx_rxint, 0, DRIVER_NAME, sport); if (retval) goto error_out1; retval = request_irq(sport->txirq, imx_txint, 0, DRIVER_NAME, sport); if (retval) goto error_out2; /* do not use RTS IRQ on IrDA */ if (!USE_IRDA(sport)) { retval = request_irq(sport->rtsirq, imx_rtsint, (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 : IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, DRIVER_NAME, sport); if (retval) goto error_out3; } } else { retval = request_irq(sport->port.irq, imx_int, 0, DRIVER_NAME, sport); if (retval) { free_irq(sport->port.irq, sport); goto error_out1; } } /* * Finally, clear and enable interrupts */ writel(USR1_RTSD, sport->port.membase + USR1); temp = readl(sport->port.membase + UCR1); temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; if (USE_IRDA(sport)) { temp |= UCR1_IREN; temp &= ~(UCR1_RTSDEN); } writel(temp, sport->port.membase + UCR1); temp = readl(sport->port.membase + UCR2); temp |= (UCR2_RXEN | UCR2_TXEN); writel(temp, sport->port.membase + UCR2); if (USE_IRDA(sport)) { /* clear RX-FIFO */ int i = 64; while ((--i > 0) && (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { barrier(); } } if (!cpu_is_mx1()) { temp = readl(sport->port.membase + UCR3); temp |= MX2_UCR3_RXDMUXSEL; writel(temp, sport->port.membase + UCR3); } if (USE_IRDA(sport)) { temp = readl(sport->port.membase + UCR4); if (sport->irda_inv_rx) temp |= UCR4_INVR; else temp &= ~(UCR4_INVR); writel(temp | UCR4_DREN, sport->port.membase + UCR4); temp = readl(sport->port.membase + UCR3); if (sport->irda_inv_tx) temp |= UCR3_INVT; else temp &= ~(UCR3_INVT); writel(temp, sport->port.membase + UCR3); } /* * Enable modem status interrupts */ spin_lock_irqsave(&sport->port.lock,flags); imx_enable_ms(&sport->port); spin_unlock_irqrestore(&sport->port.lock,flags); if (USE_IRDA(sport)) { struct imxuart_platform_data *pdata; pdata = sport->port.dev->platform_data; sport->irda_inv_rx = pdata->irda_inv_rx; sport->irda_inv_tx = pdata->irda_inv_tx; sport->trcv_delay = pdata->transceiver_delay; if (pdata->irda_enable) pdata->irda_enable(1); } return 0; error_out3: if (sport->txirq) free_irq(sport->txirq, sport); error_out2: if (sport->rxirq) free_irq(sport->rxirq, sport); error_out1: return retval; }
static int imx_startup(struct uart_port *port) { struct imx_port *sport = (struct imx_port *)port; int retval; unsigned long flags, temp; imx_setup_ufcr(sport, 0); /* disable the DREN bit (Data Ready interrupt enable) before * requesting IRQs */ temp = readl(sport->port.membase + UCR4); writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); /* * Allocate the IRQ(s) i.MX1 has three interrupts whereas later * chips only have one interrupt. */ if (sport->txirq > 0) { retval = request_irq(sport->rxirq, imx_rxint, 0, DRIVER_NAME, sport); if (retval) goto error_out1; retval = request_irq(sport->txirq, imx_txint, 0, DRIVER_NAME, sport); if (retval) goto error_out2; retval = request_irq(sport->rtsirq, imx_rtsint, (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 : IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, DRIVER_NAME, sport); if (retval) goto error_out3; } else { retval = request_irq(sport->port.irq, imx_int, 0, DRIVER_NAME, sport); if (retval) { free_irq(sport->port.irq, sport); goto error_out1; } } /* * Finally, clear and enable interrupts */ writel(USR1_RTSD, sport->port.membase + USR1); temp = readl(sport->port.membase + UCR1); temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; writel(temp, sport->port.membase + UCR1); temp = readl(sport->port.membase + UCR2); temp |= (UCR2_RXEN | UCR2_TXEN); writel(temp, sport->port.membase + UCR2); #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3 temp = readl(sport->port.membase + UCR3); temp |= UCR3_RXDMUXSEL; writel(temp, sport->port.membase + UCR3); #endif /* * Enable modem status interrupts */ spin_lock_irqsave(&sport->port.lock,flags); imx_enable_ms(&sport->port); spin_unlock_irqrestore(&sport->port.lock,flags); return 0; error_out3: if (sport->txirq) free_irq(sport->txirq, sport); error_out2: if (sport->rxirq) free_irq(sport->rxirq, sport); error_out1: return retval; }