void init_rf (RF_PULSE_T *rf, char rfName[MAX_STR], double pw, double flip,
double rof1, double rof2)
{
if ((ix > 1) && !sglarray) {
rf->flip = flip;
return;
}
initRf(rf);
strcpy(rf->pulseName,rfName);
strcpy(rf->rfcoil,rfcoil);
rf->rfDuration = shapelistpw(rfName,pw); /* Round to 200ns resolution*/
rf->flip = flip;
rf->flipmult = 1.0; /* default to 1, programmer can reassign in sequence */
rf->rof1 = rof1;
rf->rof2 = rof2;
readRfPulse(rf);
switch (rf->error) {
case ERR_RF_SHAPE_MISSING:
sgl_abort_message("ERROR: Can not find RF shape '%s.RF'",rfName);
break;
case ERR_RF_HEADER_ENTRIES:
sgl_abort_message("ERROR rf shape '%s': incorrect header information",rfName);
break;
default:
break;
}
if ((rf->header.rfFraction < 0) || (rf->header.rfFraction > 1))
sgl_abort_message("ERROR rf shape '%s': RF Fraction must be between 0 and 1",rfName);
}
void shape_rf (RF_PULSE_T *rf, char rfBase[MAX_STR], char rfName[MAX_STR], double pw, double flip,
double rof1, double rof2)
{
if ((ix > 1) && !sglarray) {
rf->flip = flip;
return;
}
initRf(rf);
strcpy(rf->pulseBase,rfBase);
strcpy(rf->pulseName,rfName);
strcpy(rf->rfcoil,rfcoil);
rf->rfDuration = pw;
rf->flip = flip;
rf->flipmult = 1.0;
rf->rof1 = rof1;
rf->rof2 = rof2;
/* Generate the pulse shape if rf->pulseName is appropriate */
genRf(rf);
/* If the pulse shape has not been generated proceed as for init_rf */
switch (rf->type) {
case RF_NULL:
rf->rfDuration = shapelistpw(rfName,pw); /* Round to 200ns resolution*/
readRfPulse(rf);
/* Set actual bandwidth according to pulse duration */
if ((FP_LT(rf->flip,FLIPLIMIT_LOW)) || (FP_GT(rf->flip,FLIPLIMIT_HIGH)))
/* use excitation bandwidth */
rf->bandwidth = rf->header.bandwidth/rf->rfDuration;
else
/* use inversion bandwidth */
rf->bandwidth = rf->header.inversionBw/rf->rfDuration;
break;
default:
/* Even though shape is properly quantized for some reason we need to
use shapelistpw to round to 200ns resolution, otherwise duration may
be significantly wrong ?? */
rf->rfDuration = shapelistpw(rf->pulseName,pw);
break;
}
switch (rf->error) {
case ERR_RF_SHAPE_MISSING:
sgl_abort_message("ERROR: Can not find RF shape '%s.RF'",rfName);
break;
case ERR_RF_HEADER_ENTRIES:
sgl_abort_message("ERROR rf shape '%s': incorrect header information",rfName);
break;
default:
break;
}
if ((rf->header.rfFraction < 0) || (rf->header.rfFraction > 1))
sgl_abort_message("ERROR rf shape '%s': RF Fraction must be between 0 and 1",rfName);
}
////////////////////////////////////////////////////////////////////////////////
/// @brief Application main function.
////////////////////////////////////////////////////////////////////////////////
void main(void) {
// Initializations
SET_MAIN_CLOCK_SOURCE(CRYSTAL);
SET_MAIN_CLOCK_SPEED(MHZ_26);
CLKCON = (CLKCON & 0xC7);
init_peripherals();
P0 &= ~0x40; // Pulse the Codec Reset line (high to low, low to high)
P0 |= 0x40;
init_codec(); // Initilize the Codec
INT_SETFLAG(INUM_DMA, INT_CLR); // clear the DMA interrupt flag
I2SCFG0 |= 0x01; // Enable the I2S interface
DMA_SET_ADDR_DESC0(&DmaDesc0); // Set up DMA configuration table for channel 0
DMA_SET_ADDR_DESC1234(&DmaDesc1_4[0]); // Set up DMA configuration table for channels 1 - 4
dmaMemtoMem(AF_BUF_SIZE); // Set up DMA Channel 0 for memmory to memory data transfers
initRf(); // Set radio base frequency and reserve DMA channels 1 and 2 for RX/TX buffers
dmaAudio(); // Set up DMA channels 3 and 4 for the Audio In/Out buffers
DMAIRQ = 0;
DMA_ARM_CHANNEL(4); // Arm DMA channel 4
macTimer3Init();
INT_ENABLE(INUM_T1, INT_ON); // Enable Timer 1 interrupts
INT_ENABLE(INUM_DMA, INT_ON); // Enable DMA interrupts
INT_GLOBAL_ENABLE(INT_ON); // Enable Global interrupts
MAStxData.macPayloadLen = TX_PAYLOAD_LEN;
MAStxData.macField = MAC_ADDR;
while (1) { // main program loop
setChannel(channel[band][ActiveChIdx]); // SetChannel will set the MARCSTATE to IDLE
ActiveChIdx = (ActiveChIdx + 1) & 0x03;
SCAL(); // Start PLL calibration at new channel
if ((P1 & 0x08) != aux_option_status) { // if the 'SEL AUX IN' option bit has changed state
if ((P1 & 0x08) == 0) { // SEL AUX IN has changed state to true
I2Cwrite(MIC1LP_LEFTADC, 0xFC); // Disconnect MIC1LP/M from the Left ADC, Leave Left DAC enabled
I2Cwrite(MIC2L_MIC2R_LEFTADC, 0x2F); // Connect AUX In (MIC2L) to Left ADC
I2Cwrite(LEFT_ADC_PGA_GAIN, 0x00); // Set PGA gain to 0 dB
aux_option_status &= ~0x08;
}
else { // SEL AUX IN has changed state to false
I2Cwrite(MIC2L_MIC2R_LEFTADC, 0xFF); // Disconnect AUX In (MIC2L) from Left ADC
I2Cwrite(MIC1LP_LEFTADC, 0x84); // Connect the internal microphone to the Left ADC using differential inputs (gain = 0 dB); Power Up the Left ADC
I2Cwrite(LEFT_ADC_PGA_GAIN, 0x3C); // Enable PGA and set gain to 30 dB
aux_option_status |= 0x08;
}
}
if ((P1 & 0x04) != agc_option_status) { // if the 'ENA AGC' option bit has changed state
if ((P1 & 0x04) == 0) { // ENA AGC has changed state to true
I2Cwrite(LEFT_AGC_CNTRL_A, 0x90); // Left AGC Control Register A - Enable, set target level to -8 dB
I2Cwrite(LEFT_AGC_CNTRL_B, 0xC8); // Left AGC Control Register B - Set maximum gain to to 50 dB
I2Cwrite(LEFT_AGC_CNTRL_C, 0x00); // Left AGC Control Register C - Disable Silence Detection
agc_option_status &= ~0x04;
}
else { // SEL AUX IN has changed state to false
I2Cwrite(LEFT_AGC_CNTRL_A, 0x10); // Left AGC Control Register A - Disable
agc_option_status |= 0x04;
}
}
// Check the band selection bits
band = 2; // if the switch is not in position 1 or 2, in must be in position 3
if ((P1 & 0x10) == 0) // check if switch is in position 1
band = 0;
else if ((P0 & 0x04) == 0) // check if switch is in position 2
band = 1;
// Now wait for the "audio frame ready" signal
while (audioFrameReady == FALSE); // Wait until an audioframe is ready to be transmitted
audioFrameReady = FALSE; // Reset the flag
// Move data from the CODEC (audioOut) buffer to the TX buffer using DMA Channel 0
SET_WORD(DmaDesc0.SRCADDRH, DmaDesc0.SRCADDRL, audioOut[activeOut]);
SET_WORD(DmaDesc0.DESTADDRH, DmaDesc0.DESTADDRL, MAStxData.payload);
DmaDesc0.SRCINC = SRCINC_1; // Increment Source address
DMAARM |= DMA_CHANNEL_0;
DMAREQ |= DMA_CHANNEL_0; // Enable memory-to-memory transfer using DMA channel 0
while ((DMAARM & DMA_CHANNEL_0) > 0); // Wait for transfer to complete
while (MARCSTATE != 0x01); // Wait for calibration to complete
P2 |= 0x08; // Debug - Set P2_3 (TP2)
rfSendPacket(MASTER_TX_TIMEOUT_WO_CALIB);
P2 &= ~0x08; // Debug - Reset P2_3 (TP2)
} // end of 'while (1)' loop
}
