//Initialize all the peripherals
void init_peripherals(void)
{
//Hardware modules:
init_systick_timer(); //SysTick timer
init_usart1(2000000); //USART1 (RS-485 #1)
init_usart6(2000000); //USART6 (RS-485 #2)
init_rs485_outputs();
init_leds();
init_switches();
init_dio(); //All inputs by default
init_adc1();
init_spi4(); //Plan
//init_spi5(); //FLASH
//init_spi6(); //Expansion
init_i2c1();
init_imu();
init_adva_fc_pins();
init_pwr_out();
//Software:
init_master_slave_comm();
//All RGB LEDs OFF
LEDR(0); LEDG(0); LEDB(0);
//Default analog input states:
set_default_analog();
}
int main()
{
unsigned int k, j;
unsigned long start_sectorptr; /* Facilitates abortion of last recording trigger. */
////////////////////
// Default values
////////////////////
posttrigger_len = 0;
trigger_hit = 0;
first_int_since_trigger = 1;
for (k = 0; k < 4; k++) {
*(SRAMchipW+k) = 0x8000 + (0x2<<k);
*(SRAMchipR+k) = 0x8200 + (0x2<<k);
}
DMAptr_at_trigger=0;
sram_unit=0;
batstack_id = 0x05;
build_date = 0x50E5; // 2010 July 5
swidth_mactive = 0xAF;
sample_period = 375;
sectorptr = 2;
dmablock_flag = 0;
TRISG &= 0xfc3f;
INTCON1bits.NSTDIS = 1; /* Disable nested interrupts */
/*
* Switch to our desired clock, achieving Tcy = 25 ns.
*
*/
__asm__ volatile ( "disi #0x3fff" ); // Disable (priority level < 7) interrupts during clock switch
PLLFBD = 0x1E;
CLKDIV = 0x0; /* In particular, PLLPRE := 0, PLLPOST := 0, DOZEN := 0. */
__asm__ volatile ( "mov #0x78, w0\n\t"
"mov #0x9A, w1\n\t"
"mov #0x46, w2\n\t"
"mov #0x57, w3\n\t"
"mov #0x3, w4\n\t"
"mov #0x1, w5\n\t"
"mov #0x743, w7\n\t"
"mov #0x742, w6\n\t"
"mov.b w0, [w7]\n\t"
"mov.b w1, [w7]\n\t"
"mov.b w4, [w7]\n\t"
"mov.b w2, [w6]\n\t"
"mov.b w3, [w6]\n\t"
"mov.b w5, [w6]\n\t" );
while (OSCCONbits.OSWEN) ;
__asm__ volatile ( "disi #0x0" ); // Re-enable interrupts
// Trigger button setting (and LEDs)
TRISC = 0x0002;
PORTC = 0;
/* Disable all A/D pins except AN0:3
This is done in init_adc1 but seems cleaner here. */
AD1PCFGH = 0xFFFF;
AD1PCFGL = 0xFFF0;
init_SRAM_write();
num_dmablocks = NUM_DMABLOCKS_PER_SRAM;
init_adc1();
init_dma5(); /* Initialize DMA channel to buffer ADC data in conversion order. */
AD1CON1bits.ADON = 1; /* Start the ADC1 module! */
/* Initialize the A/D converter module; note that we must not initialize
the ADC module before the DMA channel 5 is ready; otherwise we may
fall out of sync (and thus invalidate the assumption that DMA transfer
block addresses are such that
0 mod 4 is CH0,
1 mod 4 is CH1,
2 mod 4 is CH2, and
3 mod 4 is CH3, i.e. interleaved).
*/
initspi();
if (initsd() < 0) {
// Failed to initialize SD card; give up
printLEDnum( 0x4 );
while (1) ;
}
sdcard_read_hdr();
DMAptr_at_trigger = 0;
while (1) {
/* Verify space availability on SD card. This is a poor method
to track or restrict space usage and only used temporarily
for quick testing. */
if (total_trials > 64) {
toggle_LEDs_forever();
}
/* Wait for trigger. */
printLEDnum( 0x00 );
k = 0;
j = 0;
while (!TRIGGER) { /* Wait for trigger (Port C1 pin driven up to Vdd). */
k++;
if (k > 1000) {
j++;
k = 0;
if (j > 1000) {
LED2 ^= 1; /* Waiting for trigger indicator */
j = 0;
}
}
}
__asm__ volatile ( "DISI #0x3FFF" );
/* Temporarily block interrupts with priority level < 7;
in particular, DMA5 channel block transfer handler. */
DMAptr_at_trigger = DSADR; /* Trigger point. */
DMAptr_at_trigger &= 0x07F8; /* Clear lower 3 bits to ensure
alignment with 4-sample group
(because there are 4 mic
channels). */
trigger_hit = 1; /* Flag that we just received trigger signal */
LED1 = 1; /* Echo this on pin RC3. */
__asm__ volatile ( "DISI #0" ); /* Unblock all interrupts. */
while (trigger_hit) ;
LED1 = 0; /* Indicate recording complete. */
first_int_since_trigger = 1; /* In preparation for the next trial capture. */
/* Add this trial to the SD card.
*/
start_sectorptr = sectorptr;
sdcard_transfer_data();
sdcard_hdr_addtrial( start_sectorptr, 0xDEAD,
0xBEEF,
posttrigger_len );
/* Note that we do not update the SD card header with this new
trial until after copying has completed. This is to improve
confidence in results and more easily allow trial recording
abortions. */
__asm__ volatile ( "DISI #0x3FFF" );
init_SRAM_write(); /* Reset DMA/SRAM unit writing related stuff. */
num_dmablocks = NUM_DMABLOCKS_PER_SRAM;
DMAptr_at_trigger = 0; /* Unlock SRAM units, begin capturing A/D data stream again. */
__asm__ volatile ( "DISI #0" );
}
AD1CON1bits.ADON = 0;
DMA5CONbits.CHEN = 0;
printLEDword( DMAptr_at_trigger );
return 0;
}
