static inline void setup_transfer(struct floppy_state *fs)
{
int n;
struct swim3 __iomem *sw = fs->swim3;
struct dbdma_cmd *cp = fs->dma_cmd;
struct dbdma_regs __iomem *dr = fs->dma;
struct request *req = fs->cur_req;
if (blk_rq_cur_sectors(req) <= 0) {
swim3_warn("%s", "Transfer 0 sectors ?\n");
return;
}
if (rq_data_dir(req) == WRITE)
n = 1;
else {
n = fs->secpertrack - fs->req_sector + 1;
if (n > blk_rq_cur_sectors(req))
n = blk_rq_cur_sectors(req);
}
swim3_dbg(" setup xfer at sect %d (of %d) head %d for %d\n",
fs->req_sector, fs->secpertrack, fs->head, n);
fs->scount = n;
swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0);
out_8(&sw->sector, fs->req_sector);
out_8(&sw->nsect, n);
out_8(&sw->gap3, 0);
out_le32(&dr->cmdptr, virt_to_bus(cp));
if (rq_data_dir(req) == WRITE) {
/* Set up 3 dma commands: write preamble, data, postamble */
init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble));
++cp;
init_dma(cp, OUTPUT_MORE, bio_data(req->bio), 512);
++cp;
init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble));
} else {
init_dma(cp, INPUT_LAST, bio_data(req->bio), n * 512);
}
++cp;
out_le16(&cp->command, DBDMA_STOP);
out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
in_8(&sw->error);
out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
if (rq_data_dir(req) == WRITE)
out_8(&sw->control_bis, WRITE_SECTORS);
in_8(&sw->intr);
out_le32(&dr->control, (RUN << 16) | RUN);
/* enable intr when transfer complete */
out_8(&sw->intr_enable, TRANSFER_DONE);
out_8(&sw->control_bis, DO_ACTION);
set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */
}
static inline void setup_transfer(struct floppy_state *fs)
{
int n;
struct swim3 __iomem *sw = fs->swim3;
struct dbdma_cmd *cp = fs->dma_cmd;
struct dbdma_regs __iomem *dr = fs->dma;
if (fd_req->current_nr_sectors <= 0) {
printk(KERN_ERR "swim3: transfer 0 sectors?\n");
return;
}
if (rq_data_dir(fd_req) == WRITE)
n = 1;
else {
n = fs->secpertrack - fs->req_sector + 1;
if (n > fd_req->current_nr_sectors)
n = fd_req->current_nr_sectors;
}
fs->scount = n;
swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0);
out_8(&sw->sector, fs->req_sector);
out_8(&sw->nsect, n);
out_8(&sw->gap3, 0);
out_le32(&dr->cmdptr, virt_to_bus(cp));
if (rq_data_dir(fd_req) == WRITE) {
/* Set up 3 dma commands: write preamble, data, postamble */
init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble));
++cp;
init_dma(cp, OUTPUT_MORE, fd_req->buffer, 512);
++cp;
init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble));
} else {
init_dma(cp, INPUT_LAST, fd_req->buffer, n * 512);
}
++cp;
out_le16(&cp->command, DBDMA_STOP);
out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
in_8(&sw->error);
out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
if (rq_data_dir(fd_req) == WRITE)
out_8(&sw->control_bis, WRITE_SECTORS);
in_8(&sw->intr);
out_le32(&dr->control, (RUN << 16) | RUN);
/* enable intr when transfer complete */
out_8(&sw->intr_enable, TRANSFER_DONE);
out_8(&sw->control_bis, DO_ACTION);
set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */
}
/*
* Finds a free channel, and binds the requested device to it.
* Returns the allocated channel number, or negative on error.
* Requests the DMA done IRQ if irqhandler != NULL.
*/
int request_au1000_dma(int dev_id, const char *dev_str,
irqreturn_t (*irqhandler)(int, void *, struct pt_regs *),
unsigned long irqflags,
void *irq_dev_id)
{
struct dma_chan *chan;
const struct dma_dev *dev;
int i, ret;
#if defined(CONFIG_SOC_AU1100)
if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
return -EINVAL;
#else
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
return -EINVAL;
#endif
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
if (au1000_dma_table[i].dev_id < 0)
break;
}
if (i == NUM_AU1000_DMA_CHANNELS)
return -ENODEV;
chan = &au1000_dma_table[i];
if (dev_id >= DMA_NUM_DEV) {
dev_id -= DMA_NUM_DEV;
dev = &dma_dev_table_bank2[dev_id];
} else {
dev = &dma_dev_table[dev_id];
}
if (irqhandler) {
chan->irq = AU1000_DMA_INT_BASE + i;
chan->irq_dev = irq_dev_id;
if ((ret = request_irq(chan->irq, irqhandler, irqflags,
dev_str, chan->irq_dev))) {
chan->irq = 0;
chan->irq_dev = NULL;
return ret;
}
} else {
chan->irq = 0;
chan->irq_dev = NULL;
}
// fill it in
chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN;
chan->dev_id = dev_id;
chan->dev_str = dev_str;
chan->fifo_addr = dev->fifo_addr;
chan->mode = dev->dma_mode;
/* initialize the channel before returning */
init_dma(i);
return i;
}
/** Initialize the analog subsystem.
Initialize the ADC and start hardware scan for all sensors.
*/
void analog_init() {
if (NUM_TEMP_SENSORS) { // At least one channel in use.
init_dma();
init_analog();
}
}
static int init(int channel)
{
char temp[64];
pci_bus_cookie *current_cookie = kmalloc(sizeof(pci_bus_cookie));
current_cookie->channel = channel;
pci_init(current_cookie);
//return -1;
bus_cookies[channel] = current_cookie;
current_cookie->dma_supported = true;
sprintf(temp, "pci_ide_sem%d", channel);
current_cookie->bus_semaphore = sem_create(1, temp);
if(current_cookie->bus_semaphore < 0)
{
kfree(current_cookie);
return -1;
}
TRACE(("trying to discover devices on channel %d\n",channel));
if(channel==0)
{
current_cookie->base_reg = 0x1f0;
current_cookie->status_reg = 0x3f0;
}
else
{
current_cookie->base_reg = 0x170;
current_cookie->status_reg = 0x370;
}
if(ide_raw_init(current_cookie)==0)
{
int current_drive;
init_dma(current_cookie);
for(current_drive=0;current_drive<2;current_drive++)
{
int i = 0;
current_cookie->drives[current_drive] = NULL;
TRACE(("trying to discover device %d/%d\n",channel,current_drive));
while(ide_drives[i]!=NULL)
{
void *drive_cookie = ide_drives[i]->init_drive(&pci_bus,current_cookie,channel,current_drive);
if(drive_cookie!=NULL)
{
TRACE(("trying to discover device %d/%d is a %s\n",channel,current_drive,ide_drives[i]->device_name));
current_cookie->drives[current_drive] = ide_drives[i];
current_cookie->drive_cookie[current_drive] = drive_cookie;
init_ide_struct(channel,current_drive,-1);
TRACE(("done discovering device\n"));
TRACE(("Cookie for interrupt is %p\n",current_cookie));
int_set_io_interrupt_handler(14,&ide_interrupt_handler, current_cookie);
break;
}
i++;
}
}
return 0;
}
return -1;
}
int main(int argc, const char **argv)
{
char hostname[32];
//Getting my ID
if (argc >= 3) {
strncpy(hostname, argv[1], 32);
myid = atoi(argv[1]);
} else {
gethostname(hostname, 32);
if ( strstr(hostname, "nohost") != NULL ) {
myid = atoi(hostname+strlen("nohost"));
} else if( strstr(hostname, "bdbm") != NULL ) {
myid = atoi(hostname+strlen("bdbm"));
} else {
myid = 1;
}
}
fprintf(stderr, "Main: hostname=%s myid=%d\n", hostname, myid);
init_dma();
long actualFrequency=0;
long requestedFrequency=1e9/MainClockPeriod;
int status = setClockFrequency(0, requestedFrequency, &actualFrequency);
fprintf(stderr, "Requested Freq: %5.2f, Actual Freq: %5.2f, status=%d\n"
,(double)requestedFrequency*1.0e-6
,(double)actualFrequency*1.0e-6,status);
//Start ext aurora
auroraifc_start(myid);
device->start(0);
device->setDebugVals(0,0); //flag, delay
device->debugDumpReq(0);
sleep(1);
device->debugDumpReq(0);
sleep(1);
//void local_test(bool check, int read_repeat, int debug_lvl )
// local_test(true, 1, 5);
// LOG(0, "Press any key to continue..\n");
//gets(str);
//void one_to_many_test(bool check, int read_repeat, int debug_lvl, int accessNode)
one_to_many_test(true, 1, 5, 1);
LOG(0, "Press any key to continue..\n");
// gets(str);
//void many_to_many_test(bool check, int test_repeat, int read_repeat, int debug_lvl)
// many_to_many_test(true, 1, 10, 5);
}
static void mainproc(void *arg)
{
Dynamic *dynamicp;
Gfx *glistp;
Control cont;
init_dma();
init_task();
init_framebuffer();
read_rom( _staticSegmentStart,
_staticSegmentRomStart, _staticSegmentRomEnd );
read_rom( _dkSegmentStart, _dkSegmentRomStart, _dkSegmentRomEnd );
read_rom( _dk7SegmentStart, _dk7SegmentRomStart, _dk7SegmentRomEnd );
read_rom( _roadSegmentStart, _roadSegmentRomStart,
_roadSegmentRomEnd );
read_rom( _l2_tvSegmentStart, _l2_tvSegmentRomStart,
_l2_tvSegmentRomEnd );
init_controlers( &cont );
game_init();
while (1)
{
read_controler( &cont );
dynamicp = &dynamic;
guOrtho( &dynamicp->projection,
-(float) SCREEN_WD / 2.0F, (float) SCREEN_WD / 2.0F,
-(float) SCREEN_HT / 2.0F, (float) SCREEN_HT / 2.0F,
1.0F, 10.0F, 1.0F );
guRotate( &dynamicp->modeling, 0.0F, 0.0F, 0.0F, 1.0F );
glistp = dynamicp->glist;
/* rcp rdp & color frame buffer initialize */
glistp = init_rcprdp( glistp, (char *)_staticSegmentStart, draw_buffer );
glistp = clear_cfb( glistp );
/* game main */
glistp = game_main( glistp, &cont );
gDPFullSync(glistp++);
gSPEndDisplayList(glistp++);
assert((glistp - dynamicp->glist) < GLIST_LEN);
start_task( glistp, dynamicp );
swap_framebuffer( draw_buffer );
draw_buffer ^= 1;
}
}
int main(int argc, const char **argv)
{
//Getting my ID
char hostname[32];
gethostname(hostname,32);
char* userhostid = getenv("BDBM_ID");
if ( userhostid != NULL ) {
myid = atoi(userhostid);
} else {
myid = atoi(hostname+strlen("bdbm"));
if ( strstr(hostname, "bdbm") == NULL ) {
myid = 1;
}
}
fprintf(stderr, "Main: myid=%d\n", myid);
init_dma();
//Start ext aurora
auroraifc_start(myid);
device->start(0);
device->setDebugVals(0,0); //flag, delay
device->debugDumpReq(0);
sleep(1);
device->debugDumpReq(0);
sleep(1);
char str[10];
//void local_test(bool check, int read_repeat, int debug_lvl )
local_test(true, 1, 5);
LOG(0, "Press any key to continue..\n");
gets(str);
/*
//void one_to_many_test(bool check, int read_repeat, int debug_lvl, int accessNode)
one_to_many_test(true, 1, 5, 1);
LOG(0, "Press any key to continue..\n");
gets(str);
*/
//void many_to_many_test(bool check, int test_repeat, int read_repeat, int debug_lvl)
many_to_many_test(true, 1, 10, 5);
}
static void au1000_dma_start(struct audio_stream *stream)
{
if (!stream->buffer)
return;
init_dma(stream->dma);
if (get_dma_active_buffer(stream->dma) == 0) {
clear_dma_done0(stream->dma);
set_dma_addr0(stream->dma, stream->buffer->start);
set_dma_count0(stream->dma, stream->period_size >> 1);
set_dma_addr1(stream->dma, stream->buffer->next->start);
set_dma_count1(stream->dma, stream->period_size >> 1);
} else {
/*
* bcm6352_init_dev: initialize Ethernet Switch device,
* allocate Tx/Rx buffer descriptors pool, Tx control block pool.
*/
static int bcm6352_init_dev(bcm6352enet_softc *softc)
{
unsigned long i, j;
unsigned char *p = NULL;
/* make sure emac clock is on */
INTC->blkEnables |= (ESWITCH_CLK_EN | EPHY_CLK_EN);
/* setup buffer/pointer relationships here */
softc->nrRxBds = NR_RX_BDS;
softc->rxBufLen = ENET_MAX_MTU_SIZE;
/* init rx/tx dma channels */
softc->dmaChannels = (DmaChannel *)(DMA_BASE);
softc->rxDma = &softc->dmaChannels[EMAC_RX_CHAN];
softc->txDma = &softc->dmaChannels[EMAC_TX_CHAN];
p = (unsigned char *) (((uint32_t) softc->txBuf + 0x10) & ~0x0f);
softc->txBufPtr = (unsigned char *)K0_TO_K1((uint32_t) p);
p = (unsigned char *) (((uint32_t) softc->rxMem + 0x10) & ~0x0f);
softc->rxBds = (DmaDesc *)K0_TO_K1((uint32_t) p);
p += softc->nrRxBds * sizeof(DmaDesc);
softc->rxBuffers = (unsigned char *) K0_TO_PHYS((uint32_t) p);
/* initialize rx ring pointer variables. */
softc->rxBdAssignPtr = softc->rxBdReadPtr = softc->rxBds;
softc->rxFirstBdPtr = softc->rxBds;
softc->rxLastBdPtr = softc->rxFirstBdPtr + softc->nrRxBds - 1;
/* init the receive buffer descriptor ring */
for (i = 0, j = (unsigned long) softc->rxBuffers; i < softc->nrRxBds;
i++, j += softc->rxBufLen)
{
(softc->rxFirstBdPtr + i)->length = softc->rxBufLen;
(softc->rxFirstBdPtr + i)->address = j;
(softc->rxFirstBdPtr + i)->status = DMA_OWN;
}
softc->rxLastBdPtr->status = DMA_OWN | DMA_WRAP;
/* init dma registers */
init_dma(softc);
/* init switch control registers */
init_mii(softc);
softc->rxDma->cfg |= DMA_ENABLE;
/* if we reach this point, we've init'ed successfully */
return 0;
}
void main(void)
{
uint32_t i;
RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
GPIOB->MODER = 0x00005555;
GPIOB->ODR = 0x0000;
NVIC_EnableIRQ(15);
init_dac();
init_dma();
init_tim2();
for(;;) {
GPIOB->ODR = DMA1->ISR;
}
}
/**
* \brief Run WM8731 module unit tests.
*/
int main(void)
{
const usart_serial_options_t uart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.paritytype = CONF_TEST_PARITY
};
/* Initialize the system. */
sysclk_init();
board_init();
#ifdef BOARD_AT24C_TWI_INSTANCE
/* reset EEPROM state to release TWI */
at24cxx_reset();
#endif
/* Configure console UART. */
sysclk_enable_peripheral_clock(CONSOLE_UART_ID);
stdio_serial_init(CONF_TEST_UART, &uart_serial_options);
/* Initial the WM8731 to DAC */
init_dac();
/* Initial the ssc interface */
init_ssc();
/* Configure DMA */
init_dma();
/* Define all the test cases */
DEFINE_TEST_CASE(wm8731_transfer_test, NULL, run_wm8731_transfer_test,
NULL, "WM8731 transfer test.");
/* Put test case addresses in an array */
DEFINE_TEST_ARRAY(wm8731_tests) = {
&wm8731_transfer_test,
};
/* Define the test suite */
DEFINE_TEST_SUITE(wm8731_suite, wm8731_tests,
"SAM WM8731 module test suite");
/* Run all tests in the test suite */
test_suite_run(&wm8731_suite);
while (1) {
/* Busy-wait forever */
}
}
static void
au1000_dma_start(audio_stream_t *stream)
{
snd_pcm_substream_t *substream = stream->substream;
snd_pcm_runtime_t *runtime = substream->runtime;
unsigned long flags, dma_start;
int i;
au1000_period_t * pointer;
if (stream->buffer == NULL) {
dma_start = virt_to_phys(runtime->dma_area);
stream->period_size = frames_to_bytes(runtime,
runtime->period_size);
stream->buffer = kmalloc(sizeof(au1000_period_t), GFP_KERNEL);
pointer = stream->buffer;
for (i = 0 ; i < runtime->periods ; i++) {
pointer->start = (u32)(dma_start +
(i * stream->period_size));
pointer->relative_end = (u32)
(((i+1) * stream->period_size) - 0x1);
if ( i < runtime->periods - 1) {
pointer->next = kmalloc(sizeof(au1000_period_t)
, GFP_KERNEL);
pointer = pointer->next;
}
}
pointer->next = stream->buffer;
spin_lock_irqsave(&stream->dma_lock, flags);
init_dma(stream->dma);
if (get_dma_active_buffer(stream->dma) == 0) {
clear_dma_done0(stream->dma);
set_dma_addr0(stream->dma, stream->buffer->start);
set_dma_count0(stream->dma, stream->period_size >> 1);
set_dma_addr1(stream->dma, stream->buffer->next->start);
set_dma_count1(stream->dma, stream->period_size >> 1);
} else {
// Entry point for Power On Self Test (POST) - the BIOS initilization
// phase. This function makes the memory at 0xc0000-0xfffff
// read/writable and then calls dopost().
void VISIBLE32FLAT
handle_post(void)
{
debug_serial_setup();
dprintf(1, "Start bios (version %s)\n", VERSION);
// Enable CPU caching
setcr0(getcr0() & ~(CR0_CD|CR0_NW));
// Clear CMOS reboot flag.
outb_cmos(0, CMOS_RESET_CODE);
// Make sure legacy DMA isn't running.
init_dma();
// Check if we are running under Xen.
xen_probe();
// Allow writes to modify bios area (0xf0000)
make_bios_writable();
// Now that memory is read/writable - start post process.
dopost();
}
int main()
{
int status;
int temp,i,j;
//static int Result1[SIZE];
init_platform();
// Initialize DMA
init_dma();
//get data from the PL block to DDR RAM
status = XAxiDma_SimpleTransfer(&AxiDma, 0xa000000, 1023,XAXIDMA_DEVICE_TO_DMA);
/* Wait for transfer to be done */
while(XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA));
j=0;
// read data from DDR ram to UART
for(i=0;i<=1023;i+=1)
{
temp = Xil_In32(0xa000000+j);
xil_printf("DDR address 0x%x",0xa0000000+i);
xil_printf(" contains %d\n\r",temp);
j+=4;
}
return 0;
}
int main(void) {
volatile int16_t* samples;
unsigned int i;
DISABLE_GLOBAL_INT();
/* stop watchdog timer */
WDTCTL = WDTPW +WDTHOLD;
/* SET CPU to 5MHz */
/* max DCO
MCLK = DCOCLK
SMCLK = DCOCLK
ACLK = 8KHz
*/
DCOCTL = DCO0 + DCO1 + DCO2;
BCSCTL1 = RSEL0 + RSEL1 + RSEL2 + XT2OFF;
BCSCTL2 = 0x00;
delay_us(10000);
/* activate Active Mode */
__bic_SR_register(LPM4_bits);
/* set LEDs when loaded */
P5SEL = 0x00;
P5DIR = 0x70;
LED_RED_ON();
LED_GREEN_OFF();
LED_BLUE_OFF();
check_for_clock();
init_usb_serial();
#ifdef USE_DMA
init_dma(&g_sample_flag);
#endif
#ifdef TX
init_adc(&g_sample_flag);
#else
init_dac();
#endif
init_rf(RF_CHANNEL, PAN_ID, NODE_ADDR, &g_sample_flag);
debug_print("Successfully booted.\n");
/* set LEDS to signalize finished initilizing */
LED_RED_OFF();
ENABLE_GLOBAL_INT();
#ifdef TX
/* TX */
while(1) {
if(g_sample_flag == 1) {
g_sample_flag = 0;
#ifdef USE_DMA
/* get samples */
samples = get_samples_dma();
#else
/* get samples */
samples = get_samples();
#endif
/* send oder radio, 2*num_words */
send_rf_data(RF_RX_ADDR, (uint8_t*) samples, NUM_SAMPLES*2);
}
/* reset WDT */
WDTCTL = WDTPW + WDTCNTCL;
}
#else
/* RX */
while(1) {
if(g_sample_flag == 1) {
g_sample_flag = 0;
samples = get_samples_rf();
#if 0
uint8_t err = 0;
for(i = 0; i < NUM_SAMPLES; ++i) {
//samples[i] = 4095-7*i;
usb_printf("%d\n", samples[i]);
//if( ((uint16_t) samples[i]) > 4095) {
// usb_printf("i=%u\n", i);
// ++err;
//}
}
usb_printf("#error: %u\n", err);
usb_printf("\n\n");
#endif
set_dma_data(samples, NUM_SAMPLES);
}
/* reset WDT */
WDTCTL = WDTPW + WDTCNTCL;
}
#endif
return 0;
}
static int internal_open(bcmenet_softc * softc)
{
int i;
void *p;
/* make sure emac clock is on */
PERF->blkEnables |= EMAC_CLK_EN;
/* init rx/tx dma channels */
softc->dmaCtrl = (DmaRegs *)(EMAC_DMA_BASE);
softc->rxDma = &softc->dmaCtrl->chcfg[EMAC_RX_CHAN];
softc->txDma = &softc->dmaCtrl->chcfg[EMAC_TX_CHAN];
p = KMALLOC( NR_TX_BDS * sizeof(DmaDesc), CACHE_ALIGN );
if( p == NULL ) {
xprintf( "BCM6348 : Failed to allocate txBds memory.\n" );
return -1;
}
INVAL_RANGE(p, NR_TX_BDS * sizeof(DmaDesc));
softc->txBds = (DmaDesc *)K0_TO_K1((uint32) p);
p = KMALLOC( NR_RX_BDS * sizeof(DmaDesc), CACHE_ALIGN );
if( p== NULL ) {
xprintf( "BCM6348 : Failed to allocate rxBds memory.\n" );
KFREE( (void *)(softc->txBds) );
softc->txBds = NULL;
return -1;
}
INVAL_RANGE(p, NR_RX_BDS * sizeof(DmaDesc));
softc->rxBds = (DmaDesc *)K0_TO_K1((uint32) p);
softc->rxBuffers = (uint32_t)KMALLOC( NR_RX_BDS * ENET_BUF_SIZE, CACHE_ALIGN );
if( softc->rxBuffers == NULL ) {
xprintf( "BCM6348 : Failed to allocate RxBuffer memory.\n" );
KFREE( (void *)(softc->txBds) );
softc->txBds = NULL;
KFREE( (void *)(softc->rxBds) );
softc->rxBds = NULL;
return -1;
}
INVAL_RANGE(softc->rxBuffers, NR_RX_BDS * ENET_BUF_SIZE);
softc->txBuffers = (uint32_t)KMALLOC( NR_TX_BDS * ENET_BUF_SIZE, CACHE_ALIGN );
if( softc->txBuffers == NULL ) {
xprintf( "BCM6348 : Failed to allocate txBuffer memory.\n" );
KFREE( (void *)(softc->rxBuffers) );
softc->rxBuffers = NULL;
KFREE( (void *)(softc->txBds) );
softc->txBds = NULL;
KFREE( (void *)(softc->rxBds) );
softc->rxBds = NULL;
return -1;
}
INVAL_RANGE(softc->txBuffers, NR_TX_BDS * ENET_BUF_SIZE);
/* Init the Receive Buffer Descriptor Ring. */
softc->rxFirstBdPtr = softc->rxBdReadPtr = softc->rxBds;
softc->rxLastBdPtr = softc->rxBds + NR_RX_BDS - 1;
for(i = 0; i < NR_RX_BDS; i++) {
(softc->rxBds + i)->status = DMA_OWN;
(softc->rxBds + i)->length = ENET_BUF_SIZE;
(softc->rxBds + i)->address = softc->rxBuffers + i * ENET_BUF_SIZE;
(softc->rxBds + i)->address = K1_TO_PHYS( (softc->rxBds + i)->address );
softc->dmaCtrl->flowctl_ch1_alloc = 1;
}
softc->rxLastBdPtr->status |= DMA_WRAP;
/* Init Transmit Buffer Descriptor Ring. */
softc->txFirstBdPtr = softc->txNextBdPtr = softc->txBds;
softc->txLastBdPtr = softc->txBds + NR_TX_BDS - 1;
for(i = 0; i < NR_TX_BDS; i++) {
(softc->txBds + i)->status = 0;
(softc->txBds + i)->length = 0;
(softc->txBds + i)->address = softc->txBuffers + i * ENET_BUF_SIZE;
(softc->txBds + i)->address = K1_TO_PHYS( (softc->txBds + i)->address );
}
softc->txLastBdPtr->status = DMA_WRAP;
/* init dma registers */
init_dma(softc);
/* init enet control registers */
if (init_emac(softc))
return -1;
getMacAddress(softc->hwaddr);
bcm6348_write_mac_address( softc, softc->hwaddr);
softc->rxDma->cfg |= DMA_ENABLE;
return 0;
}
int main(void)
{
int i, spi_timeout;
unsigned long counter;
/* Disable JTAG port so we get our I/O pins back */
DDPCONbits.JTAGEN = 0;
/* Enable optimal performance */
SYSTEMConfigPerformance(GetSystemClock());
/* Use 1:1 CPU Core:Peripheral clocks */
OSCSetPBDIV(OSC_PB_DIV_1);
/* configure the core timer roll-over rate */
OpenCoreTimer(CORE_TICK_RATE);
/* set up the core timer interrupt */
mConfigIntCoreTimer((CT_INT_ON | CT_INT_PRIOR_6 | CT_INT_SUB_PRIOR_0));
/* enable multi vector interrupts */
INTConfigureSystem(INT_SYSTEM_CONFIG_MULT_VECTOR);
INTEnableInterrupts();
map_peripherals();
init_io_ports();
configure_pwm();
init_spi();
init_dma();
/* wait until tx buffer is filled up */
while (!SPI2STATbits.SPITBF);
reset_board();
spi_data_ready = 0;
spi_timeout = 0;
counter = 0;
/* enable watchdog */
WDTCONSET = 0x8000;
/* main loop */
while (1) {
if (spi_data_ready) {
spi_data_ready = 0;
/* the first element received is a command string */
switch (rxBuf[0]) {
case 0x5453523E: /* >RST */
reset_board();
break;
case 0x314D433E: /* >CM1 */
stepgen_update_input((const void *)&rxBuf[1]);
stepgen_get_position((void *)&txBuf[1]);
break;
case 0x324D433E: /* >CM2 */
update_outputs(rxBuf[1]);
update_pwm_duty((uint32_t *)&rxBuf[2]);
txBuf[1] = read_inputs();
break;
case 0x4746433E: /* >CFG */
stepgen_update_stepwidth(rxBuf[1]);
update_pwm_period(rxBuf[2]);
stepgen_reset();
break;
case 0x5453543E: /* >TST */
for (i=0; i<BUFSIZE; i++)
txBuf[i] = rxBuf[i] ^ ~0;
break;
}
}
/* if rx buffer is half-full, update the integrity check.
There isn't enough time if we wait for complete transfer */
if (DCH0INTbits.CHDHIF) {
DCH0INTCLR = 1<<4; /* clear flag */
txBuf[0] = rxBuf[0] ^ ~0;
}
/* if rx buffer is full, data from spi bus is ready */
if (DCH0INTbits.CHBCIF) {
DCH0INTCLR = 1<<3; /* clear flag */
spi_data_ready = 1;
spi_timeout = SPI_TIMEOUT;
}
/* reset the board if there is no SPI activity */
if (spi_timeout)
spi_timeout--;
if (spi_timeout == 1) {
DCH0ECONSET=BIT_6; /* abort DMA transfers */
DCH1ECONSET=BIT_6;
init_spi();
init_dma();
reset_board();
/* wait until tx buffer is filled up */
while (!SPI2STATbits.SPITBF);
}
/* blink onboard led */
if (!(counter++ % (spi_timeout ? 0x10000 : 0x40000))) {
LED_TOGGLE;
}
/* keep alive */
WDTCONSET = 0x01;
}
return 0;
}
// Program entry point
int main()
{
init_platform();
int status;
//Initialize uart port
status = init_uart(uart);
if(status == XST_FAILURE){
printf("ERROR INITIALIZING UART PORT...EXITING...\n");
exit(-1);
}
// Initialize the (simple) DMA engine
status = init_dma(&axiDma);
if (status != XST_SUCCESS) {
exit(-1);
}
//Disabling the cache
Xil_DCacheDisable();
Xil_ICacheDisable();
int i=0;
int j = 0;
//always available when started
float* in = malloc(conv_channel * conv_in_x * conv_in_y * sizeof(float));
float* result = malloc(output_size * sizeof(float));
//receiving result from PL
//status = XAxiDma_SimpleTransfer(&axiDma,(u32)result,sizeof(float) * output_size,
// XAXIDMA_DEVICE_TO_DMA);
for(i=0;i<10;i++){
// result[i]= i;
printf("%f\n",(float)result[i]);
}
while(j++<5){
/*for(i=0;i<10;i++){
printf("%f\n",(float)result[i]);
}*/
for(i=0;i<256;i++){
in[i] = (float)/*i/100;*/((i*j)+2+i)/1000;
}
//receiving input
//uart_receive(in,(conv_channel*conv_in_x*conv_in_y)*sizeof(float));
//printf("test is %c\n",test);
printf("*** ATTEMPT NUMBER %d ***\n",j);
//flushing the relative cache range
//Xil_DCacheFlushRange((unsigned)in,(conv_channel*conv_in_x*conv_in_y) * sizeof(float));
//Handling the DMA to PL input transfer
status = XAxiDma_SimpleTransfer(&axiDma,(u32)in,sizeof(float) * (conv_channel*conv_in_x*conv_in_y),
XAXIDMA_DMA_TO_DEVICE);
usleep(3000000);
/*printf("BEFORE\n");
for(i=0;i<10;i++){
printf("%f\n",(float)result[i]);
}*/
//receiving result from PL
status = XAxiDma_SimpleTransfer(&axiDma,(u32)result,sizeof(float) * output_size,
XAXIDMA_DEVICE_TO_DMA);
//invalidating the relative cache range in order to receive again
//Xil_DCacheInvalidateRange((unsigned)result,output_size * sizeof(float));
//printing results on screen
//printf("AFTER\n");
for(i=0;i<10;i++){
// result[i]= i;
printf("%f\n",(float)result[i]);
}
//sending the results to the UART port
//uart_send(result,sizeof(float)*output_size);
//XUartPs_Send(&uart,(u8)result,sizeof(float) * output_size);
//resetting the DMA because SDK sucks
XAxiDma_Reset(&axiDma);
}
free(in);
free(result);
return 0;
}
int do_dma_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong addr, dest, count , tempaddr;
int size;
unsigned int ChannelNo;
struct dma_device_cfg configuration = {
MEMORY_DMA_REQ,
(DMA_WRAP_1|DMA_BURST_8|DMA_SIZE_32|DMA_SG_MODE|DMA_SW_REQ),
Source1,
Destination1,
} ;
if (argc != 4) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/* Check for size specification.
*/
if ((size = cmd_get_data_size(argv[0], 4)) < 0)
return 1;
addr = simple_strtoul(argv[1], NULL, 16);
addr += base_address;
dest = simple_strtoul(argv[2], NULL, 16);
dest += base_address;
count = simple_strtoul(argv[3], NULL, 16);
if (count == 0) {
puts ("Zero length ???\n");
return 1;
}
count *= size;
#ifndef CFG_NO_FLASH
/* check if we are copying to Flash */
if ( (addr2info(dest) != NULL)
#ifdef CONFIG_HAS_DATAFLASH
&& (!addr_dataflash(addr))
#endif
) {
int rc;
puts ("Copy to Flash... ");
rc = flash_write ((char *)addr, dest, count);
if (rc != 0) {
flash_perror (rc);
return (1);
}
puts ("done\n");
return 0;
}
#endif
init_dma();
if(addr >= 0xFE000000){
*(volatile unsigned int *)(0xD8330000) = 0x33013301;
*(volatile unsigned int *)(0xD8330008) = 0x10004;
*(volatile unsigned int *)(0xD8330010) = 0x10004;
*(volatile unsigned int *)(0xD8330020) = 0x809;
*(volatile unsigned int *)(0xD8330028) = 0x809;
request_dma(&ChannelNo, "dmacp", I2S_TX_DMA_REQ);
}
else
request_dma(&ChannelNo, "dmacp", MEMORY_DMA_REQ);
if(addr >= 0xFE000000){
configuration.DeviceReqType = I2S_TX_DMA_REQ;
configuration.DefaultCCR = (DMA_WRAP_1|DMA_BURST_8|DMA_SIZE_32|DMA_SG_MODE|DMA_UP_MEMREG_EN|DEVICE_TO_MEM);
tempaddr = addr;
addr = dest;
dest = tempaddr;
}
init_descriptstack(ChannelNo);
setup_dma(ChannelNo, configuration);
//printf("ISR ch%d = %x\n", ChannelNo, pDma_Reg->DMA_ISR);
//printf("IER ch%d = %x\n", ChannelNo, pDma_Reg->DMA_IER);
//printf("CCR ch%d = %x\n", ChannelNo, pDma_Reg->DMA_CCR_CH[ChannelNo]);
//{
// start_dma(ChannelNo, (unsigned long)addr, (unsigned long)dest, count);
// printf("DMA%d : handle irq begin\n", ChannelNo);
// handle_dma_irq(ChannelNo);
// printf("DMA%d : handle irq OK\n", ChannelNo);
/*******************************************
* wait for dma transfer complete and terminal count
********************************************/
// while (1) {
// if (dma_busy(ChannelNo) != 1)
// break;
// }
// printf("DMA%d : no busy\n", ChannelNo);
// while (1) {
// if (dma_complete(ChannelNo) == 0)
// break;
// }
//}
handle_transfer(ChannelNo, (unsigned long)addr, (unsigned long)dest, count);
reset_descriptstack(ChannelNo);
printf("DMA%d : transfer OK\n", ChannelNo);
return 0;
}
