static void __init common_init_irq(void (*srm_dev_int)(unsigned long v)) { init_i8259a_irqs(); if (alpha_using_srm) { alpha_mv.device_interrupt = srm_dev_int; init_srm_irqs(35, 0); } else { long i; outb(0xff, 0x804); outb(0xff, 0x805); outb(0xff, 0x806); for (i = 16; i < 35; ++i) { irq_set_chip_and_handler(i, &cabriolet_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } common_init_isa_dma(); setup_irq(16+4, &isa_cascade_irqaction); }
static void __init alcor_init_irq(void) { long i; if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */ *(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */ for (i = 16; i < 48; ++i) { /* On Alcor, at least, lines 20..30 are not connected and can generate spurious interrupts if we turn them on while IRQ probing. */ if (i >= 16+20 && i <= 16+30) continue; irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq; init_i8259a_irqs(); common_init_isa_dma(); setup_irq(16+31, &isa_cascade_irqaction); }
static void __init common_init_irq(void (*srm_dev_int)(unsigned long v, struct pt_regs *r)) { init_i8259a_irqs(); if (alpha_using_srm) { alpha_mv.device_interrupt = srm_dev_int; init_srm_irqs(35, 0); } else { long i; outb(0xff, 0x804); outb(0xff, 0x805); outb(0xff, 0x806); for (i = 16; i < 35; ++i) { irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; irq_desc[i].handler = &cabriolet_irq_type; } } common_init_isa_dma(); setup_irq(16+4, &isa_cascade_irqaction); }
static void __init ruffian_init_irq(void) { /* Invert 6&7 for i82371 */ *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb(); *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */ outb(0x11,0xA0); outb(0x08,0xA1); outb(0x02,0xA1); outb(0x01,0xA1); outb(0xFF,0xA1); outb(0x11,0x20); outb(0x00,0x21); outb(0x04,0x21); outb(0x01,0x21); outb(0xFF,0x21); /* Finish writing the 82C59A PIC Operation Control Words */ outb(0x20,0xA0); outb(0x20,0x20); init_i8259a_irqs(); /* Not interested in the bogus interrupts (0,3,6), NMI (1), HALT (2), flash (5), or 21142 (8). */ init_pyxis_irqs(0x16f0000); common_init_isa_dma(); }
static void __init miata_init_irq(void) { if (alpha_using_srm) alpha_mv.device_interrupt = miata_srm_device_interrupt; #if 0 /* These break on MiataGL so we'll try not to do it at all. */ *(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb(); /* ISA/NMI HI */ *(vulp)PYXIS_RT_COUNT = 0UL; mb(); /* clear count */ #endif init_i8259a_irqs(); /* Not interested in the bogus interrupts (3,10), Fan Fault (0), NMI (1), or EIDE (9). We also disable the risers (4,5), since we don't know how to route the interrupts behind the bridge. */ init_pyxis_irqs(0x63b0000); common_init_isa_dma(); setup_irq(16+2, &halt_switch_irqaction); /* SRM only? */ setup_irq(16+6, &timer_cascade_irqaction); }
static void __init alcor_init_irq(void) { long i; if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; *(vuip)GRU_INT_MASK = 0; mb(); /* */ *(vuip)GRU_INT_EDGE = 0; mb(); /* */ *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* */ *(vuip)GRU_INT_CLEAR = 0; mb(); /* */ for (i = 16; i < 48; ++i) { /* */ if (i >= 16+20 && i <= 16+30) continue; irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq; init_i8259a_irqs(); common_init_isa_dma(); setup_irq(16+31, &isa_cascade_irqaction); }
static void __init rawhide_init_irq(void) { struct pci_controller *hose; long i; mcpcia_init_hoses(); /* Clear them all; only hoses that exist will be non-zero. */ for (i = 0; i < MCPCIA_MAX_HOSES; i++) cached_irq_masks[i] = 0; for (hose = hose_head; hose; hose = hose->next) { unsigned int h = hose->index; unsigned int mask = hose_irq_masks[h]; cached_irq_masks[h] = mask; *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0; } for (i = 16; i < 128; ++i) { irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; irq_desc[i].chip = &rawhide_irq_type; } init_i8259a_irqs(); common_init_isa_dma(); }
static void __init nautilus_init_irq(void) { if (alpha_using_srm) { alpha_mv.device_interrupt = srm_device_interrupt; } init_i8259a_irqs(); common_init_isa_dma(); }
static void __init jensen_init_irq(void) { init_i8259a_irqs(); irq_desc[1].handler = &jensen_local_irq_type; irq_desc[4].handler = &jensen_local_irq_type; irq_desc[3].handler = &jensen_local_irq_type; irq_desc[7].handler = &jensen_local_irq_type; irq_desc[9].handler = &jensen_local_irq_type; common_init_isa_dma(); }
static void __init titan_legacy_init_irq(void) { /* init the legacy dma controller */ outb(0, DMA1_RESET_REG); outb(0, DMA2_RESET_REG); outb(DMA_MODE_CASCADE, DMA2_MODE_REG); outb(0, DMA2_MASK_REG); /* init the legacy irq controller */ init_i8259a_irqs(); /* init the titan irqs */ titan_init_irq(); }
static void __init rx164_init_irq(void) { long i; rx164_update_irq_hw(0); for (i = 16; i < 40; ++i) { irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } init_i8259a_irqs(); common_init_isa_dma(); setup_irq(16+20, &isa_cascade_irqaction); }
static void __init clipper_init_irq(void) { outb(0, DMA1_RESET_REG); outb(0, DMA2_RESET_REG); outb(DMA_MODE_CASCADE, DMA2_MODE_REG); outb(0, DMA2_MASK_REG); if (alpha_using_srm) alpha_mv.device_interrupt = clipper_srm_device_interrupt; tsunami_update_irq_hw(0); init_i8259a_irqs(); init_tsunami_irqs(&clipper_irq_type, 24, 63); }
static void __init mikasa_init_irq(void) { long i; if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; mikasa_update_irq_hw(0); for (i = 16; i < 32; ++i) { irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; irq_desc[i].chip = &mikasa_irq_type; } init_i8259a_irqs(); common_init_isa_dma(); }
static void __init mikasa_init_irq(void) { long i; if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; mikasa_update_irq_hw(0); for (i = 16; i < 32; ++i) { irq_to_desc(i)->status |= IRQ_LEVEL; set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq); } init_i8259a_irqs(); common_init_isa_dma(); }
static void __init wildfire_init_irq_per_pca(int qbbno, int pcano) { int i, irq_bias; unsigned long io_bias; static struct irqaction isa_enable = { handler: no_action, name: "isa_enable", }; irq_bias = qbbno * (WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA) + pcano * WILDFIRE_IRQ_PER_PCA; /* Only need the following for first PCI bus per PCA. */ io_bias = WILDFIRE_IO(qbbno, pcano<<1) - WILDFIRE_IO_BIAS; #if 0 outb(0, DMA1_RESET_REG + io_bias); outb(0, DMA2_RESET_REG + io_bias); outb(DMA_MODE_CASCADE, DMA2_MODE_REG + io_bias); outb(0, DMA2_MASK_REG + io_bias); #endif #if 0 /* ??? Not sure how to do this, yet... */ init_i8259a_irqs(); /* ??? */ #endif for (i = 0; i < 16; ++i) { if (i == 2) continue; irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; irq_desc[i+irq_bias].handler = &wildfire_irq_type; } irq_desc[36+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; irq_desc[36+irq_bias].handler = &wildfire_irq_type; for (i = 40; i < 64; ++i) { irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; irq_desc[i+irq_bias].handler = &wildfire_irq_type; } setup_irq(32+irq_bias, &isa_enable); }
static void __init wildfire_init_irq(void) { int qbbno, pcano; #if 1 wildfire_init_irq_hw(); init_i8259a_irqs(); #endif for (qbbno = 0; qbbno < WILDFIRE_MAX_QBB; qbbno++) { if (WILDFIRE_QBB_EXISTS(qbbno)) { for (pcano = 0; pcano < WILDFIRE_PCA_PER_QBB; pcano++) { if (WILDFIRE_PCA_EXISTS(qbbno, pcano)) { wildfire_init_irq_per_pca(qbbno, pcano); } } } } }
static void __init miata_init_irq(void) { if (alpha_using_srm) alpha_mv.device_interrupt = miata_srm_device_interrupt; init_i8259a_irqs(); /* Not interested in the bogus interrupts (3,10), Fan Fault (0), NMI (1), or EIDE (9). We also disable the risers (4,5), since we don't know how to route the interrupts behind the bridge. */ init_pyxis_irqs(0x63b0000); common_init_isa_dma(); setup_irq(16+2, &halt_switch_irqaction); /* SRM only? */ setup_irq(16+6, &timer_cascade_irqaction); }
static void __init sx164_init_irq(void) { outb(0, DMA1_RESET_REG); outb(0, DMA2_RESET_REG); outb(DMA_MODE_CASCADE, DMA2_MODE_REG); outb(0, DMA2_MASK_REG); if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; init_i8259a_irqs(); /* */ if (alpha_using_srm) init_srm_irqs(40, 0x3f0000); else init_pyxis_irqs(0xff00003f0000UL); setup_irq(16+6, &timer_cascade_irqaction); }
static void __init sx164_init_irq(void) { outb(0, DMA1_RESET_REG); outb(0, DMA2_RESET_REG); outb(DMA_MODE_CASCADE, DMA2_MODE_REG); outb(0, DMA2_MASK_REG); if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; init_i8259a_irqs(); /* Not interested in the bogus interrupts (0,3,4,5,40-47), NMI (1), or HALT (2). */ if (alpha_using_srm) init_srm_irqs(40, 0x3f0000); else init_pyxis_irqs(0xff00003f0000); setup_irq(16+6, &timer_cascade_irqaction); }
static void __init wildfire_init_irq_per_pca(int qbbno, int pcano) { int i, irq_bias; static struct irqaction isa_enable = { .handler = no_action, .name = "isa_enable", }; irq_bias = qbbno * (WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA) + pcano * WILDFIRE_IRQ_PER_PCA; #if 0 unsigned long io_bias; /* Only need the following for first PCI bus per PCA. */ io_bias = WILDFIRE_IO(qbbno, pcano<<1) - WILDFIRE_IO_BIAS; outb(0, DMA1_RESET_REG + io_bias); outb(0, DMA2_RESET_REG + io_bias); outb(DMA_MODE_CASCADE, DMA2_MODE_REG + io_bias); outb(0, DMA2_MASK_REG + io_bias); #endif #if 0 /* ??? Not sure how to do this, yet... */ init_i8259a_irqs(); /* ??? */ #endif for (i = 0; i < 16; ++i) { if (i == 2) continue; irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type, handle_level_irq); irq_set_status_flags(i + irq_bias, IRQ_LEVEL); } irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type, handle_level_irq); irq_set_status_flags(36 + irq_bias, IRQ_LEVEL); for (i = 40; i < 64; ++i) { irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type, handle_level_irq); irq_set_status_flags(i + irq_bias, IRQ_LEVEL); } setup_irq(32+irq_bias, &isa_enable); } static void __init wildfire_init_irq(void) { int qbbno, pcano; #if 1 wildfire_init_irq_hw(); init_i8259a_irqs(); #endif for (qbbno = 0; qbbno < WILDFIRE_MAX_QBB; qbbno++) { if (WILDFIRE_QBB_EXISTS(qbbno)) { for (pcano = 0; pcano < WILDFIRE_PCA_PER_QBB; pcano++) { if (WILDFIRE_PCA_EXISTS(qbbno, pcano)) { wildfire_init_irq_per_pca(qbbno, pcano); } } } } }