void goom_set_resolution (guint32 resx, guint32 resy, int cinemascope) { free (pixel); free (back); if (cinemascope) c_black_height = resy / 8; else c_black_height = 0; c_offset = c_black_height * resx; c_resoly = resy - c_black_height * 2; resolx = resx; resoly = resy; buffsize = resx * resy; pixel = (guint32 *) malloc (buffsize * sizeof (guint32) + 128); memset (pixel, 0, buffsize * sizeof (guint32) + 128); back = (guint32 *) malloc (buffsize * sizeof (guint32) + 128); memset (back, 0, buffsize * sizeof (guint32) + 128); p1 = (guint32 *) ((1 + ((uintptr_t) (pixel)) / 128) * 128); p2 = (guint32 *) ((1 + ((uintptr_t) (back)) / 128) * 128); init_ifs (resx, c_resoly); goom_lines_set_res (gmline1, resx, c_resoly); goom_lines_set_res (gmline2, resx, c_resoly); }
void goom_init (guint32 resx, guint32 resy, int cinemascope) { #ifdef VERBOSE printf ("GOOM: init (%d, %d);\n", resx, resy); #endif if (cinemascope) c_black_height = resy / 5; else c_black_height = 0; resolx = resx; resoly = resy; buffsize = resx * resy; c_offset = c_black_height * resx; c_resoly = resy - c_black_height * 2; pixel = (guint32 *) malloc (buffsize * sizeof (guint32) + 128); back = (guint32 *) malloc (buffsize * sizeof (guint32) + 128); //RAND_INIT (); srand ((guint32) pixel); if (!rand_tab) rand_tab = (int *) malloc (NB_RAND * sizeof(int)) ; rand_pos = 1 ; while (rand_pos != 0) rand_tab [rand_pos++] = rand () ; cycle = 0; p1 = (guint32 *) ((1 + ((unsigned int) (pixel)) / 128) * 128); p2 = (guint32 *) ((1 + ((unsigned int) (back)) / 128) * 128); init_ifs (resx, c_resoly); gmline1 = goom_lines_init (resx, c_resoly, GML_HLINE, c_resoly, GML_BLACK, GML_CIRCLE, 0.4f * (float) c_resoly, GML_VERT); gmline2 = goom_lines_init (resx, c_resoly, GML_HLINE, 0, GML_BLACK, GML_CIRCLE, 0.2f * (float) c_resoly, GML_RED); // font_height = NULL; // font_width = NULL; // font_chars = NULL; gfont_load (); tentacle_new (); }
int main (int argc, char **argv) { int c; char *tapname = NULL; char *vnetname = "802ip"; me = argv[0]; setvbuf (stdout, NULL, _IONBF, 0); init_iface_drivers (); while ((c = getopt (argc, argv, "dI:i:")) != -1) { switch (c) { case 'd': debug = 1; break; case 'i': tapname = optarg; break; case 'I': vnetname = optarg; break; default: usage (); break; } } init_ifs (tapname, vnetname); if (!debug) if (daemon (0, 0) < 0) { perror ("daemon"); exit (1); } event_loop (); return 0; }
/** * mtrr_bp_init - initialize mtrrs on the boot CPU * * This needs to be called early; before any of the other CPUs are * initialized (i.e. before smp_init()). * */ void __init mtrr_bp_init(void) { u32 phys_addr; init_ifs(); phys_addr = 32; if (cpu_has_mtrr) { mtrr_if = &generic_mtrr_ops; size_or_mask = 0xff000000; /* 36 bits */ size_and_mask = 0x00f00000; phys_addr = 36; /* * This is an AMD specific MSR, but we assume(hope?) that * Intel will implement it to when they extend the address * bus of the Xeon. */ if (cpuid_eax(0x80000000) >= 0x80000008) { phys_addr = cpuid_eax(0x80000008) & 0xff; /* CPUID workaround for Intel 0F33/0F34 CPU */ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 == 0xF && boot_cpu_data.x86_model == 0x3 && (boot_cpu_data.x86_mask == 0x3 || boot_cpu_data.x86_mask == 0x4)) phys_addr = 36; size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); size_and_mask = ~size_or_mask & 0xfffff00000ULL; } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && boot_cpu_data.x86 == 6) { /* * VIA C* family have Intel style MTRRs, * but don't support PAE */ size_or_mask = 0xfff00000; /* 32 bits */ size_and_mask = 0; phys_addr = 32; } } else { switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: if (cpu_has_k6_mtrr) { /* Pre-Athlon (K6) AMD CPU MTRRs */ mtrr_if = mtrr_ops[X86_VENDOR_AMD]; size_or_mask = 0xfff00000; /* 32 bits */ size_and_mask = 0; } break; case X86_VENDOR_CENTAUR: if (cpu_has_centaur_mcr) { mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; size_or_mask = 0xfff00000; /* 32 bits */ size_and_mask = 0; } break; case X86_VENDOR_CYRIX: if (cpu_has_cyrix_arr) { mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; size_or_mask = 0xfff00000; /* 32 bits */ size_and_mask = 0; } break; default: break; } } if (mtrr_if) { set_num_var_ranges(); init_table(); if (use_intel()) { get_mtrr_state(); if (mtrr_cleanup(phys_addr)) { changed_by_mtrr_cleanup = 1; mtrr_if->set_all(); } } } }
/** * mtrr_init - initialize mtrrs on the boot CPU * * This needs to be called early; before any of the other CPUs are * initialized (i.e. before smp_init()). * */ static int __init mtrr_init(void) { init_ifs(); if (cpu_has_mtrr) { mtrr_if = &generic_mtrr_ops; size_or_mask = 0xff000000; /* 36 bits */ size_and_mask = 0x00f00000; switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: /* The original Athlon docs said that total addressable memory is 44 bits wide. It was not really clear whether its MTRRs follow this or not. (Read: 44 or 36 bits). However, "x86-64_overview.pdf" explicitly states that "previous implementations support 36 bit MTRRs" and also provides a way to query the width (in bits) of the physical addressable memory on the Hammer family. */ if (boot_cpu_data.x86 == 15 && (cpuid_eax(0x80000000) >= 0x80000008)) { u32 phys_addr; phys_addr = cpuid_eax(0x80000008) & 0xff; size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1); size_and_mask = ~size_or_mask & 0xfff00000; } /* Athlon MTRRs use an Intel-compatible interface for * getting and setting */ break; case X86_VENDOR_CENTAUR: if (boot_cpu_data.x86 == 6) { /* VIA Cyrix family have Intel style MTRRs, but don't support PAE */ size_or_mask = 0xfff00000; /* 32 bits */ size_and_mask = 0; } break; default: break; } } else { switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: if (cpu_has_k6_mtrr) { /* Pre-Athlon (K6) AMD CPU MTRRs */ mtrr_if = mtrr_ops[X86_VENDOR_AMD]; size_or_mask = 0xfff00000; /* 32 bits */ size_and_mask = 0; } break; case X86_VENDOR_CENTAUR: if (cpu_has_centaur_mcr) { mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; size_or_mask = 0xfff00000; /* 32 bits */ size_and_mask = 0; } break; case X86_VENDOR_CYRIX: if (cpu_has_cyrix_arr) { mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; size_or_mask = 0xfff00000; /* 32 bits */ size_and_mask = 0; } break; default: break; } } printk(KERN_INFO "mtrr: v%s\n",MTRR_VERSION); if (mtrr_if) { set_num_var_ranges(); init_table(); init_other_cpus(); return sysdev_driver_register(&cpu_sysdev_class, &mtrr_sysdev_driver); } return -ENXIO; }