static int ldpaa_eth_netdev_init(struct eth_device *net_dev, phy_interface_t enet_if) { int err; struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; sprintf(net_dev->name, "DPMAC%d@%s", priv->dpmac_id, phy_interface_strings[enet_if]); net_dev->iobase = 0; net_dev->init = ldpaa_eth_open; net_dev->halt = ldpaa_eth_stop; net_dev->send = ldpaa_eth_tx; net_dev->recv = ldpaa_eth_pull_dequeue_rx; /* TODO: PHY MDIO information priv->bus = info->bus; priv->phyaddr = info->phy_addr; priv->enet_if = info->enet_if; */ if (init_phy(net_dev)) return 0; err = eth_register(net_dev); if (err < 0) { printf("eth_register() = %d\n", err); return err; } return 0; }
void maca_init(void) { reset_maca(); radio_init(); flyback_init(); init_phy(); free_head = 0; tx_head = 0; rx_head = 0; rx_end = 0; tx_end = 0; dma_tx = 0; dma_rx = 0; free_all_packets(); #if DEBUG_MACA Print_Packets("maca_init"); #endif /* initial radio command */ /* nop, promiscuous, no cca */ *MACA_CONTROL = (1 << PRM) | (NO_CCA << MODE); enable_irq(MACA); *INTFRC = (1 << INT_NUM_MACA); }
static int ldpaa_eth_netdev_init(struct eth_device *net_dev, phy_interface_t enet_if) { int err; struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; sprintf(net_dev->name, "DPMAC%d@%s", priv->dpmac_id, phy_interface_strings[enet_if]); net_dev->iobase = 0; net_dev->init = ldpaa_eth_open; net_dev->halt = ldpaa_eth_stop; net_dev->send = ldpaa_eth_tx; net_dev->recv = ldpaa_eth_pull_dequeue_rx; #ifdef CONFIG_PHYLIB err = init_phy(net_dev); if (err < 0) return err; #endif err = eth_register(net_dev); if (err < 0) { printf("eth_register() = %d\n", err); return err; } return 0; }
void maca_init(void) { reset_maca(); radio_init(); flyback_init(); init_phy(); set_channel(0); /* things get weird if you never set a channel */ set_power(0); /* set the power too --- who knows what happens if you don't */ free_head = 0; tx_head = 0; rx_head = 0; rx_end = 0; tx_end = 0; dma_tx = 0; dma_rx = 0; free_all_packets(); #if DEBUG_MACA Print_Packets("maca_init"); #endif /* initial radio command */ /* nop, promiscuous, no cca */ *MACA_CONTROL = (prm_mode << PRM) | (NO_CCA << MACA_MODE); enable_irq(MACA); *INTFRC = (1 << INT_NUM_MACA); }
static int uec_init(struct eth_device* dev, bd_t *bd) { uec_private_t *uec; int err, i; struct phy_info *curphy; uec = (uec_private_t *)dev->priv; if (uec->the_first_run == 0) { err = init_phy(dev); if (err) { printf("%s: Cannot initialize PHY, aborting.\n", dev->name); return err; } curphy = uec->mii_info->phyinfo; if (curphy->config_aneg) { err = curphy->config_aneg(uec->mii_info); if (err) { printf("%s: Can't negotiate PHY\n", dev->name); return err; } } /* Give PHYs up to 5 sec to report a link */ i = 50; do { err = curphy->read_status(uec->mii_info); udelay(100000); } while (((i-- > 0) && !uec->mii_info->link) || err); if (err || i <= 0) printf("warning: %s: timeout on PHY link\n", dev->name); uec->the_first_run = 1; } /* Set up the MAC address */ if (dev->enetaddr[0] & 0x01) { printf("%s: MacAddress is multcast address\n", __FUNCTION__); return -1; } uec_set_mac_address(uec, dev->enetaddr); err = uec_open(uec, COMM_DIR_RX_AND_TX); if (err) { printf("%s: cannot enable UEC device\n", dev->name); return -1; } phy_change(dev); return (uec->mii_info->link ? 0 : -1); }
void maca_on(void) { /* turn the radio regulators back on */ reg(0x80003048) = 0x00000f78; /* reinitialize the phy */ reset_maca(); init_phy(); enable_irq(MACA); *INTFRC = (1 << INT_NUM_MACA); }
/* Initialize device structure. Returns success if PHY * initialization succeeded (i.e. if it recognizes the PHY) */ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) { struct eth_device *dev; int i; struct tsec_private *priv; dev = (struct eth_device *)malloc(sizeof *dev); if (NULL == dev) return 0; memset(dev, 0, sizeof *dev); priv = (struct tsec_private *)malloc(sizeof(*priv)); if (NULL == priv) return 0; privlist[num_tsecs++] = priv; priv->regs = tsec_info->regs; priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; priv->flags = tsec_info->flags; sprintf(dev->name, tsec_info->devname); priv->interface = tsec_info->interface; priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); dev->iobase = 0; dev->priv = priv; dev->init = tsec_init; dev->halt = tsec_halt; dev->send = tsec_send; dev->recv = tsec_recv; #ifdef CONFIG_MCAST_TFTP dev->mcast = tsec_mcast_addr; #endif /* Tell u-boot to get the addr from the env */ for (i = 0; i < 6; i++) dev->enetaddr[i] = 0; eth_register(dev); /* Reset the MAC */ setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); /* Try to initialize PHY here, and return */ return init_phy(dev); }
static int initialize_nic(struct dm9000 *priv) { int i; dm9000_reset(priv); switch (getreg(priv, DM_ISR) >> 6) { case 0: priv->read_data = read_data_16; priv->write_data = write_data_16; priv->buswidth = 2; break; case 1: priv->read_data = read_data_32; priv->write_data = write_data_32; priv->buswidth = 4; break; case 2: priv->read_data = read_data_8; priv->write_data = write_data_8; priv->buswidth = 1; break; default: diag_printf("Unknown DM9000 bus i/f.\n"); return 0; } init_phy(priv); putreg(priv, DM_TCR, 0); putreg(priv, DM_BPTR, 0x3f); putreg(priv, DM_FCTR, 0x38); putreg(priv, DM_FCR, 0xff); putreg(priv, DM_SMCR, 0); putreg(priv, DM_NSR, NSR_WAKEST | NSR_TX1END | NSR_TX2END); putreg(priv, DM_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); // set MAC address for (i = 0; i < 6; i++) putreg(priv, DM_PAR + i, priv->mac_address[i]); // clear multicast table except for broadcast address for (i = 0; i < 6; i++) putreg(priv, DM_MAR + i, 0x00); putreg(priv, DM_MAR + 6, 0x00); putreg(priv, DM_MAR + 7, 0x80); return 1; }
static int uec_init(struct eth_device* dev, bd_t *bd) { uec_private_t *uec; int err, i; struct phy_info *curphy; #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif uec = (uec_private_t *)dev->priv; if (uec->the_first_run == 0) { #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) /* QE9 and QE12 need to be set for enabling QE MII managment signals */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); #endif err = init_phy(dev); if (err) { printf("%s: Cannot initialize PHY, aborting.\n", dev->name); return err; } curphy = uec->mii_info->phyinfo; if (curphy->config_aneg) { err = curphy->config_aneg(uec->mii_info); if (err) { printf("%s: Can't negotiate PHY\n", dev->name); return err; } } /* Give PHYs up to 5 sec to report a link */ i = 50; do { err = curphy->read_status(uec->mii_info); if (!(((i-- > 0) && !uec->mii_info->link) || err)) break; udelay(100000); } while (1); #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) /* QE12 needs to be released for enabling LBCTL signal*/ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); #endif if (err || i <= 0) printf("warning: %s: timeout on PHY link\n", dev->name); adjust_link(dev); uec->the_first_run = 1; } /* Set up the MAC address */ if (dev->enetaddr[0] & 0x01) { printf("%s: MacAddress is multcast address\n", __FUNCTION__); return -1; } uec_set_mac_address(uec, dev->enetaddr); err = uec_open(uec, COMM_DIR_RX_AND_TX); if (err) { printf("%s: cannot enable UEC device\n", dev->name); return -1; } phy_change(dev); return (uec->mii_info->link ? 0 : -1); }
int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) { struct eth_device *dev; struct fm_eth *fm_eth; int i, num = info->num; /* alloc eth device */ dev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!dev) return 0; memset(dev, 0, sizeof(struct eth_device)); /* alloc the FMan ethernet private struct */ fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth)); if (!fm_eth) return 0; memset(fm_eth, 0, sizeof(struct fm_eth)); /* save off some things we need from the info struct */ fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */ fm_eth->num = num; fm_eth->type = info->type; fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi; fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi; /* set the ethernet max receive length */ fm_eth->max_rx_len = MAX_RXBUF_LEN; /* init global mac structure */ if (!fm_eth_init_mac(fm_eth, reg)) return 0; /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */ if (fm_eth->type == FM_ETH_1G_E) sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1); else sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1); devlist[num_controllers++] = dev; dev->iobase = 0; dev->priv = (void *)fm_eth; dev->init = fm_eth_open; dev->halt = fm_eth_halt; dev->send = fm_eth_send; dev->recv = fm_eth_recv; fm_eth->dev = dev; fm_eth->bus = info->bus; fm_eth->phyaddr = info->phy_addr; fm_eth->enet_if = info->enet_if; /* startup the FM im */ if (!fm_eth_startup(fm_eth)) return 0; if (init_phy(dev)) return 0; /* clear the ethernet address */ for (i = 0; i < 6; i++) dev->enetaddr[i] = 0; eth_register(dev); return 1; }
/* return 1 if link comes up */ int open_link (void) { int packet; int n; unsigned int d32; /* Disable Ethmac interrupt in interrupt controller */ *(unsigned int *) ( ADR_AMBER_IC_IRQ0_ENABLECLR ) = 0x100; /* Set my MAC address */ d32 = self_g.mac[2]<<24|self_g.mac[3]<<16|self_g.mac[4]<<8|self_g.mac[5]; *(unsigned int *) ( ADR_ETHMAC_MAC_ADDR0 ) = d32; d32 = self_g.mac[0]<<8|self_g.mac[1]; *(unsigned int *) ( ADR_ETHMAC_MAC_ADDR1 ) = d32; if (!init_phy()) return 0; /* Write the Receive Packet Buffer Descriptor */ /* Buffer Pointer */ for (packet=0; packet<ETHMAC_RX_BUFFERS; packet++) { *(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x204 + packet*8 ) = ETHMAC_RX_BUFFER + packet * 0x1000; /* Ready Rx buffer [31:16] = length in bytes, [15] = empty [14] = Enable IRQ [13] = wrap bit */ /* set empty flag again */ if (packet == ETHMAC_RX_BUFFERS-1) /* last receive buffer ? */ /* Set wrap bit is last buffer */ *(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + packet*8 ) = 0x0000e000; else *(unsigned int *) ( ADR_ETHMAC_BDBASE + 0x200 + packet*8 ) = 0x0000c000; } /* Enable EthMac interrupts in Ethmac core */ /* Receive frame and receive error botgh enabled */ /* When a bad frame is received is still gets written to a buffer so needs to be dealt with */ *(unsigned int *) ( ADR_ETHMAC_INT_MASK ) = 0xc; /* Enable Ethmac interrupt in interrupt controller */ *(unsigned int *) ( ADR_AMBER_IC_IRQ0_ENABLESET ) = 0x100; /* Set transmit packet buffer location */ *(unsigned int *) ( ADR_ETHMAC_BDBASE + 4 ) = ETHMAC_TX_BUFFER; /* Set the ready bit, bit 15, low */ *(unsigned int *) ( ADR_ETHMAC_BDBASE + 0 ) = 0x7800; /* Enable Rx & Tx - MODER Register [15] = Add pads to short frames [13] = CRCEN [10] = Enable full duplex [7] = loopback [5] = 1 for promiscuous, 0 rx only frames that match mac address [1] = txen [0] = rxen */ *(unsigned int *) ( ADR_ETHMAC_MODER ) = 0xa423; return 1; }
int uec_initialize(int index) { struct eth_device *dev; int i; uec_private_t *uec; uec_info_t *uec_info; int err; dev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!dev) return 0; memset(dev, 0, sizeof(struct eth_device)); /* Allocate the UEC private struct */ uec = (uec_private_t *)malloc(sizeof(uec_private_t)); if (!uec) { return -ENOMEM; } memset(uec, 0, sizeof(uec_private_t)); /* Init UEC private struct, they come from board.h */ if (index == 0) { #ifdef CONFIG_UEC_ETH1 uec_info = ð1_uec_info; #endif } else if (index == 1) { #ifdef CONFIG_UEC_ETH2 uec_info = ð2_uec_info; #endif } else { printf("%s: index is illegal.\n", __FUNCTION__); return -EINVAL; } uec->uec_info = uec_info; sprintf(dev->name, "FSL UEC%d", index); dev->iobase = 0; dev->priv = (void *)uec; dev->init = uec_init; dev->halt = uec_halt; dev->send = uec_send; dev->recv = uec_recv; /* Clear the ethnet address */ for (i = 0; i < 6; i++) dev->enetaddr[i] = 0; eth_register(dev); err = uec_startup(uec); if (err) { printf("%s: Cannot configure net device, aborting.",dev->name); return err; } err = init_phy(dev); if (err) { printf("%s: Cannot initialize PHY, aborting.\n", dev->name); return err; } phy_change(dev); return 1; }
void rt_hw_eth_init(void) { u64 base_addr = Gmac_base; struct synopGMACNetworkAdapter * synopGMACadapter; static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS; rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO); rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); memset(ð_dev, 0, sizeof(eth_dev)); synopGMACadapter = (struct synopGMACNetworkAdapter * )plat_alloc_memory(sizeof (struct synopGMACNetworkAdapter)); if(!synopGMACadapter){ rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__); } memset((char *)synopGMACadapter ,0, sizeof (struct synopGMACNetworkAdapter)); synopGMACadapter->synopGMACdev = NULL; synopGMACadapter->synopGMACdev = (synopGMACdevice *) plat_alloc_memory(sizeof (synopGMACdevice)); if(!synopGMACadapter->synopGMACdev){ rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__); } memset((char *)synopGMACadapter->synopGMACdev ,0, sizeof (synopGMACdevice)); /* * Attach the device to MAC struct This will configure all the required base addresses * such as Mac base, configuration base, phy base address(out of 32 possible phys) * */ synopGMAC_attach(synopGMACadapter->synopGMACdev,(regbase + MACBASE), regbase + DMABASE, DEFAULT_PHY_BASE, mac_addr0); init_phy(synopGMACadapter->synopGMACdev); synopGMAC_reset(synopGMACadapter->synopGMACdev); /* MII setup */ synopGMACadapter->mii.phy_id_mask = 0x1F; synopGMACadapter->mii.reg_num_mask = 0x1F; synopGMACadapter->mii.dev = synopGMACadapter; synopGMACadapter->mii.mdio_read = mdio_read; synopGMACadapter->mii.mdio_write = mdio_write; synopGMACadapter->mii.phy_id = synopGMACadapter->synopGMACdev->PhyBase; synopGMACadapter->mii.supports_gmii = mii_check_gmii_support(&synopGMACadapter->mii); eth_dev.iobase = base_addr; eth_dev.name = "e0"; eth_dev.priv = synopGMACadapter; eth_dev.dev_addr[0] = mac_addr0[0]; eth_dev.dev_addr[1] = mac_addr0[1]; eth_dev.dev_addr[2] = mac_addr0[2]; eth_dev.dev_addr[3] = mac_addr0[3]; eth_dev.dev_addr[4] = mac_addr0[4]; eth_dev.dev_addr[5] = mac_addr0[5]; eth_dev.parent.parent.type = RT_Device_Class_NetIf; eth_dev.parent.parent.init = eth_init; eth_dev.parent.parent.open = eth_open; eth_dev.parent.parent.close = eth_close; eth_dev.parent.parent.read = eth_read; eth_dev.parent.parent.write = eth_write; eth_dev.parent.parent.control = eth_control; eth_dev.parent.parent.user_data = RT_NULL; eth_dev.parent.eth_tx = rt_eth_tx; eth_dev.parent.eth_rx = rt_eth_rx; eth_device_init(&(eth_dev.parent), "e0"); }
static rt_err_t eth_init(rt_device_t device ) { struct eth_device *eth_device = (struct eth_device *)device; RT_ASSERT(eth_device != RT_NULL); s32 ijk; s32 status = 0; u64 dma_addr; u32 Mac_changed = 0; struct pbuf *pbuf; u8 macaddr[6] = DEFAULT_MAC_ADDRESS; struct rt_eth_dev *dev = ð_dev; struct synopGMACNetworkAdapter *adapter = dev->priv; synopGMACdevice * gmacdev = (synopGMACdevice *)adapter->synopGMACdev; synopGMAC_reset(gmacdev); synopGMAC_attach(gmacdev,(regbase + MACBASE),(regbase + DMABASE), DEFAULT_PHY_BASE, macaddr); synopGMAC_read_version(gmacdev); synopGMAC_set_mdc_clk_div(gmacdev,GmiiCsrClk3); gmacdev->ClockDivMdc = synopGMAC_get_mdc_clk_div(gmacdev); init_phy(adapter->synopGMACdev); rt_kprintf("tx desc_queue\n"); synopGMAC_setup_tx_desc_queue(gmacdev,TRANSMIT_DESC_SIZE, RINGMODE); synopGMAC_init_tx_desc_base(gmacdev); rt_kprintf("rx desc_queue\n"); synopGMAC_setup_rx_desc_queue(gmacdev,RECEIVE_DESC_SIZE, RINGMODE); synopGMAC_init_rx_desc_base(gmacdev); DEBUG_MES("DmaRxBaseAddr = %08x\n",synopGMACReadReg(gmacdev->DmaBase,DmaRxBaseAddr)); // u32 dmaRx_Base_addr = synopGMACReadReg(gmacdev->DmaBase,DmaRxBaseAddr); // rt_kprintf("first_desc_addr = 0x%x\n", dmaRx_Base_addr); #ifdef ENH_DESC_8W synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip2 | DmaDescriptor8Words ); #else //synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip1); synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip2); #endif synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward |DmaTxSecondFrame|DmaRxThreshCtrl128); status = synopGMAC_check_phy_init(adapter); synopGMAC_mac_init(gmacdev); synopGMAC_pause_control(gmacdev); #ifdef IPC_OFFLOAD synopGMAC_enable_rx_chksum_offload(gmacdev); synopGMAC_rx_tcpip_chksum_drop_enable(gmacdev); #endif u32 skb; do{ skb = (u32)plat_alloc_memory(RX_BUF_SIZE); //should skb aligned here? if(skb == RT_NULL){ rt_kprintf("ERROR in skb buffer allocation\n"); break; } dma_addr = plat_dma_map_single(gmacdev,(void *)skb,RX_BUF_SIZE); //获取 skb 的 dma 地址 status = synopGMAC_set_rx_qptr(gmacdev,dma_addr,RX_BUF_SIZE,(u32)skb,0,0,0); if(status < 0) { rt_kprintf("status < 0!!\n"); plat_free_memory((void *)skb); } }while(status >= 0 && (status < (RECEIVE_DESC_SIZE - 1))); synopGMAC_clear_interrupt(gmacdev); synopGMAC_disable_mmc_tx_interrupt(gmacdev, 0xFFFFFFFF); synopGMAC_disable_mmc_rx_interrupt(gmacdev, 0xFFFFFFFF); synopGMAC_disable_mmc_ipc_rx_interrupt(gmacdev, 0xFFFFFFFF); // synopGMAC_disable_interrupt_all(gmacdev); synopGMAC_enable_interrupt(gmacdev, DmaIntEnable); synopGMAC_enable_dma_rx(gmacdev); synopGMAC_enable_dma_tx(gmacdev); plat_delay(DEFAULT_LOOP_VARIABLE); synopGMAC_check_phy_init(adapter); synopGMAC_mac_init(gmacdev); rt_timer_init(&dev->link_timer, "link_timer", synopGMAC_linux_cable_unplug_function, (void *)adapter, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC); rt_timer_start(&dev->link_timer); #ifdef RT_USING_GMAC_INT_MODE /* installl isr */ DEBUG_MES("%s\n", __FUNCTION__); rt_hw_interrupt_install(LS1C_MAC_IRQ, eth_rx_irq, RT_NULL, "e0_isr"); rt_hw_interrupt_umask(LS1C_MAC_IRQ); #else rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer", eth_rx_irq, (void *)adapter, 1, RT_TIMER_FLAG_PERIODIC); rt_timer_start(&dev->rx_poll_timer); #endif /*RT_USING_GMAC_INT_MODE*/ rt_kprintf("eth_inited!\n"); return RT_EOK; }
int rt_hw_eth_init(void) { u64 base_addr = Gmac_base; struct synopGMACNetworkAdapter *synopGMACadapter; static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS; int index; rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO); rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); for (index = 21; index <= 30; index++) { pin_set_purpose(index, PIN_PURPOSE_OTHER); pin_set_remap(index, PIN_REMAP_DEFAULT); } pin_set_purpose(35, PIN_PURPOSE_OTHER); pin_set_remap(35, PIN_REMAP_DEFAULT); *((volatile unsigned int *)0xbfd00424) &= ~(7 << 28); *((volatile unsigned int *)0xbfd00424) |= (1 << 30); //wl rmii memset(ð_dev, 0, sizeof(eth_dev)); synopGMACadapter = (struct synopGMACNetworkAdapter *)plat_alloc_memory(sizeof(struct synopGMACNetworkAdapter)); if (!synopGMACadapter) { rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__); } memset((char *)synopGMACadapter, 0, sizeof(struct synopGMACNetworkAdapter)); synopGMACadapter->synopGMACdev = NULL; synopGMACadapter->synopGMACdev = (synopGMACdevice *) plat_alloc_memory(sizeof(synopGMACdevice)); if (!synopGMACadapter->synopGMACdev) { rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__); } memset((char *)synopGMACadapter->synopGMACdev, 0, sizeof(synopGMACdevice)); /* * Attach the device to MAC struct This will configure all the required base addresses * such as Mac base, configuration base, phy base address(out of 32 possible phys) * */ synopGMAC_attach(synopGMACadapter->synopGMACdev, (regbase + MACBASE), regbase + DMABASE, DEFAULT_PHY_BASE, mac_addr0); init_phy(synopGMACadapter->synopGMACdev); synopGMAC_reset(synopGMACadapter->synopGMACdev); /* MII setup */ synopGMACadapter->mii.phy_id_mask = 0x1F; synopGMACadapter->mii.reg_num_mask = 0x1F; synopGMACadapter->mii.dev = synopGMACadapter; synopGMACadapter->mii.mdio_read = mdio_read; synopGMACadapter->mii.mdio_write = mdio_write; synopGMACadapter->mii.phy_id = synopGMACadapter->synopGMACdev->PhyBase; synopGMACadapter->mii.supports_gmii = mii_check_gmii_support(&synopGMACadapter->mii); eth_dev.iobase = base_addr; eth_dev.name = "e0"; eth_dev.priv = synopGMACadapter; eth_dev.dev_addr[0] = mac_addr0[0]; eth_dev.dev_addr[1] = mac_addr0[1]; eth_dev.dev_addr[2] = mac_addr0[2]; eth_dev.dev_addr[3] = mac_addr0[3]; eth_dev.dev_addr[4] = mac_addr0[4]; eth_dev.dev_addr[5] = mac_addr0[5]; eth_dev.parent.parent.type = RT_Device_Class_NetIf; eth_dev.parent.parent.init = eth_init; eth_dev.parent.parent.open = eth_open; eth_dev.parent.parent.close = eth_close; eth_dev.parent.parent.read = eth_read; eth_dev.parent.parent.write = eth_write; eth_dev.parent.parent.control = eth_control; eth_dev.parent.parent.user_data = RT_NULL; eth_dev.parent.eth_tx = rt_eth_tx; eth_dev.parent.eth_rx = rt_eth_rx; eth_device_init(&(eth_dev.parent), "e0"); eth_device_linkchange(ð_dev.parent, RT_TRUE); //linkup the e0 for lwip to check return 0; }